REVISION 1 06/15/15

7

2.5V, 3.3V DIFFERENTIAL LVPECL CLOCK DIVIDER AND BUFFER

8T73S208A-01 DATA SHEET

AC Electrical Characteristics

Symbol

NOTE 1: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device

is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal

equilibrium has been reached under these conditions.

Test Conditions

Minimum

Typical

Maximum

Units

Input Frequency

IN, nIN

1GHz

400

kHz

Buffer Additive Phase Jitter,

RMS; refer to Additive Phase

Jitter Section, measured with

FSEL[1:0] = 00

Integration Range: 12kHz – 20MHz

182

207

fs

NOTE 2: Measured from the differential input crossing point to the differential output cross point.

IN, nIN to

Qx, nQx

FSEL[1:0] = 00

350

750

fs

FSEL[1:0] = 01

500

870

ps

FSEL[1:0] = 10

550

1052

ps

FSEL[1:0] = 11

650

1230

ps

tsk(o)

NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross point.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

60

ps

tsk(p)

Pulse Skew

50

ps

tsk(pp)

NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and

with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross point.

NOTE 6: Part-to-part skew specification does not guarantee divider synchronization among devices.

500

ps

odc

NOTE 7: If FSEL[1:0] = 00 (divide-by-one), the output duty cycle will depend on the input duty cycle.

Any Frequency

50

%

48

50

52

%

48

50

52

%

48

50

52

%

Output Enable and Disable

Output Enable/ Disable State from/ to

Active/ Inactive

1µs

Output Rise/Fall Time

20% to 80%

140

205

ps

10% to 90%

180

350

ps