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UPD720122 Datasheet(PDF) 27 Page - NEC |
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UPD720122 Datasheet(HTML) 27 Page - NEC |
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27 / 82 page ![]() Data Sheet S16685EJ2V0DS 27 µPD720122 (b) CPU bus DMA single mode write transfer Symbol Parameter Min. Typ. Max. Unit T35 DMA request acknowledge setup time (WRB ↓) 0 ∞ ns T36 DMA request off time (EP2_DACKB ↓) − 54 ns T37 DMA single mode write transfer cycle time 88 ∞ ns T38 Write command width 54 ∞ ns T39 Write command inactive time 34 ∞ ns T40 Write data setup time (WRB ↑) 10 ∞ ns T41 Write data hold time (WRB ↑) 0 ∞ ns T42 EP2_TCB setup time (WRB ↓) 0 Note ns T43 EP2_TCB hold time (WRB ↓) 17 ∞ ns T44 DMA request acknowledge hold time (WRB ↑) 0 ∞ ns Note Can be input after immediately previous WRB ↑. Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF). (Overall) EP2_DRQB EP2_TCB D15 to D0 WRB EP2_DACKB t36 t38 t37 t39 t40 t41 High level N cycle N −−−− 1 cycle 1 cycle t35 t44 t40 t41 t44 |
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