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UPD720122 Datasheet(PDF) 66 Page - NEC

No. de pieza UPD720122
Descripción Electrónicos  MOS Integrated Circuit
PDF  82 Pages
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Fabricante Electrónico  NEC [NEC]
Página de inicio  http://www.nec.com/
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UPD720122 Datasheet(HTML) 66 Page - NEC

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Data Sheet S16685EJ2V0DS
66
µPD720122
Parameter
Symbol
Conditions
Min.
Max.
Unit
Device event timing
Time from internal power good to device
pulling D+/D
− beyond VIHZ (min.) (signaling
attach)
TSIGATT
100
ms
Debounce interval provided by USB system
software after attach
TATTDB
100
ms
Inter-packet delay (for low-/full-speed)
TIPD
2
Bit times
Inter-packet delay for device response
w/detachable cable for low-/full-speed
TRSPIPD1
6.5
Bit times
High-speed detection start time from
suspend
TSCA
2.5
µs
Sample time for suspend vs. reset
TCSR
100
875
µs
Power down under suspend
TSUS
10
ms
SUSPEND set time (SPNDOUT)
TSSP
0
SUSPEND clear time (RSUMOUT)
TCSP
0
Reversion time from suspend to high-speed
TRHS
1.333
µs
SUSPEND setup time (RSUMIN)
TSRW
0
RSUMIN active pulse width
TRWP
115
ms
Drive chirp K width
TCKO
1ms
Finish chirp K assertion
TFCA
7ms
Start sequencing chirp K-J-K-J-K-J
TSSC
100
µs
Finish sequencing chirp K-J
TFSC
−500
−100
µs
Detect sequencing chirp K-J width
TCSI
2.5
µs
Sample time for sequencing chirp
TSCS
1.0
2.5
ms
Reversion time to high-speed
TRHA
500
µs
High-speed detection start time
THDS
2.5
3000
µs
Reset completed time
TDRS
10
ms



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