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UPD720122 Datasheet(PDF) 34 Page - NEC |
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UPD720122 Datasheet(HTML) 34 Page - NEC |
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34 / 82 page  Data Sheet S16685EJ2V0DS 34 µPD720122 (d) CPU bus DMA demand write transfer timing Symbol Parameter Min. Typ. Max. Unit T58 DMA request acknowledge setup time (WRB ↓) 0 ∞ ns T59 DMA demand mode write transfer cycle time 72 ∞ ns T60 Write command width 38 ∞ ns T61 Write command inactive time 34 ∞ ns T62 Write data setup time (WRB ↑) 10 ∞ ns T63 Write data hold time (WRB ↑) 0 ∞ ns T64 EP2_TCB setup time (WRB ↓) 0 Note ns T65 EP2_TCB hold time (WRB ↓) 17 ∞ ns T66 DMA request off time (WRB ↑) − 60 ns T67 DMA request acknowledge hold time (WRB ↑) 0 ∞ ns T70 DMA request off time (EP2_DACKB ↓) − 38 ns T73 DMA request on time (EP2_DACKB ↑) − 88 ns T75 DMA request off time (WRB ↓) − 60 ns Note Can be input after immediately previous WRB ↑. Remark It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF). (Overall) EP2_DRQB EP2_TCB D15 to D0 WRB EP2_DACKB N cycle N −−−− 1 cycle 1 cycle t59 t60 t61 t62 t63 t66 High level t58 t67 |
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