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UPD720122 Datasheet(PDF) 30 Page - NEC

No. de pieza UPD720122
Descripción Electrónicos  MOS Integrated Circuit
PDF  82 Pages
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Fabricante Electrónico  NEC [NEC]
Página de inicio  http://www.nec.com/
Logo NEC - NEC

UPD720122 Datasheet(HTML) 30 Page - NEC

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Data Sheet S16685EJ2V0DS
30
µPD720122
(c) CPU bus DMA demand read transfer timing
Symbol
Parameter
Min.
Typ.
Max.
Unit
T45
DMA request acknowledge setup time (RDB
↓)
0
∞
ns
T46
DMA demand mode read transfer cycle time
91
∞
ns
T47
Read command width
57
∞
ns
T48
Read command inactive time
34
∞
ns
T49
Read data delay time (RDB
↓)
−
57
ns
T50
Buffer direction change time (RDB
↓)
−
14
ns
T51
Read data hold time (RDB
↑)
4
−
ns
T52
EP1_TCB setup time (RDB
↓)
0
Note
ns
T53
EP1_TCB hold time (RDB
↓)
17
∞
ns
T54
EP1_STOPB delay time (RDB
↓)
−
15
ns
T55
EP1_STOPB delay time (RDB
↑)
3
−
ns
T56
DMA request off time (RDB
↑)
−
59
ns
T57
DMA request acknowledge hold time (RDB
↑)
0
∞
ns
T69
DMA request off time (EP1_DACKB
↓)
−
38
ns
T71
DMA request off time (EP1_DACKB
↓) 1 cycle transfer
−
38
ns
T72
DMA request on time (EP1_DACKB
↑)
−
88
ns
T74
DMA request off time (RDB
↓)
−
60
ns
Note
Can be input after immediately previous RDB
↑.
Remark
It is assumed that the external pin capacitance is 15 pF (data bus = 50 pF).
(Overall)
EP1_DRQB
EP1_TCB
D15 to D0
RDB
EP1_DACKB
N cycle
N
−−−− 1 cycle
1 cycle
t46
t47
t48
t49
t51
t56
High level
t45
t50
t57
EP1_STOPB
High level
t54
t55
EP1_STOPB is not asserted in the
case of a full packet.



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