A25GFO080QL datasheet(7/58 Pages) AMICC

7 / 58 page

A25LQ080 Series

(April, 2016, Version 1.0)

AMIC Technology Corp.

OPERATING FEATURES

Page Programming

To program one data byte, two instructions are required: Write

Enable (WREN), which is one byte, and a Page Program (PP)

sequence, which consists of four bytes plus data. This is

followed by the internal Program cycle (of duration tPP).

To spread this overhead, the Page Program (PP) instruction

allows up to 256 bytes to be programmed at a time (changing

bits from 1 to 0), provided that they lie in consecutive

addresses on the same page of memory.

Dual Input Fast Program

The Dual Input Fast Program (DIFP) instruction makes it

possible to program up to 256 bytes using two input pins at

the same time (by changing bits from 1 to 0).

For optimized timings, it is recommended to use the Dual

Input Fast Program (DIFP) instruction to program all

consecutive targeted bytes in a single sequence rather to

using several Dual Input Fast Program (DIFP) sequences

each containing only a few bytes.

Quad Input Fast Program

The Quad Input Fast Program (QIFP) instruction makes it

possible to program up to 256 bytes using four input pins (IO3,

IO2, IO1, and IO0) at the same time (by changing bits from 1 to

0).

For optimized timings, it is recommended to use the Quad

Input Fast Program (QIFP) instruction to program all

consecutive targeted bytes in a single sequence rather to

using several Quad Input Fast Program (QIFP) sequences

each containing only a few bytes.

Sector Erase, Block Erase, and Chip Erase

The Page Program (PP) instruction, Dual Input Fast Program

(DIFP) instruction, and Quad Input Fast Program (QIFP)

instruction allow bits to be reset from 1 to 0. Before this can

be applied, the bytes of memory need to have been erased to

all 1s (FFh). This can be achieved, a sector at a time, using

the Sector Erase (SE) instruction, a block at a time, using the

Block Erase (BE) instruction, or throughout the entire memory,

using the Chip Erase (CE) instruction. This starts an internal

Erase cycle (of duration tSE, tBE, or tCE).

The Erase instruction must be preceded by a Write Enable

(WREN) instruction.

Polling During a Write, Program or Erase Cycle

A further improvement in the time to Write Status Register

(WRSR), Program OTP (POTP), Program (PP, DIFP, QIFP),

or Erase (SE, BE, or CE) can be achieved by not waiting for

the worst case delay (tW, tPP, tSE, tBE, tCE). The Write In

Progress (WIP) bit is provided in the Status Register so that

the application program can monitor its value, polling it to

establish when the previous Write cycle, Program cycle or

Erase cycle is complete.

Active Power, Stand-by Power and Deep Power-Down

Modes

When Chip Select (

S ) is Low, the device is enabled, and in

the Active Power mode.

When Chip Select (

S ) is High, the device is disabled, but

could remain in the Active Power mode until all internal cycles

have completed (Program, Erase, Write Status Register). The

device then goes in to the Stand-by Power mode. The device

consumption drops to ICC1.

The Deep Power-down mode is entered when the specific

instruction (the Deep Power-down Mode (DP) instruction) is

executed. The device consumption drops further to ICC2. The

device remains in this mode until another specific instruction

(the Release from Deep Power-down Mode and Read

Electronic Signature (RES) instruction) is executed.

All other instructions are ignored while the device is in the

Deep Power-down mode. This can be used as an extra

software protection mechanism, when the device is not in

active use, to protect the device from inadvertent Write,

Program or Erase instructions.

Status Register

The Status Register contains a number of status and control

bits that can be read or set (as appropriate) by specific

instructions. See Read Status Register (RDSR) for a detailed

description of the Status Register bits.

Protection Modes

The environments where non-volatile memory devices are

used can be very noisy. No SPI device can operate correctly

in the presence of excessive noise. To help combat this, the

A25LQ080 boasts the following data protection mechanisms:

Power-On Reset and an internal timer (tPUW) can provide

protection against inadvertent changes while the power

supply is outside the operating specification.

Program, Erase and Write Status Register instructions are

checked that they consist of a number of clock pulses that

is a multiple of eight, before they are accepted for

execution.

All instructions that modify data must be preceded by a

Write Enable (WREN) instruction to set the Write Enable

Latch (WEL) bit. This bit is returned to its reset state by

the following events:

- Power-up

- Write Disable (WRDI) instruction completion

- Write Status Register (WRSR) instruction completion

- Program OTP (POTP) instruction completion

- Page Program (PP) instruction completion

- Dual Input Fast Program (DIFP) instruction completion

- Quad input Fast Program (QIFP) instruction completion

- Sector Erase (SE) instruction completion

- Block Erase (BE) instruction completion

- Chip Erase (CE) instruction completion

The Block Protect (BP2, BP1, BP0) bits conjunction with

Sector Protect (SEC) bit , Top/Bottom (TB) bit and

Complement Protect (CMP) bit allow part of the memory to

be configured as read-only. This is the Software Protected

Mode (SPM).

The Write Protect (

W ) signal allows the Block Protect

(BP2, BP1, BP0) bits, Sector Protect (SEC) bit,

Top/Bottom (TB) bit, All Protect (APT), Complement

Protect (CMP) bit and Status Register Protect (SRP0) bit

to be protected. This is the Hardware Protected Mode

(HPM).

In addition to the low power consumption feature, the

Deep Power-down mode offers extra software protection

from inadvertent Write, Program and Erase instructions, as

all instructions are ignored except one particular instruction

(the Release from Deep Power-down instruction).

A25GFO080QL Datasheet(PDF) 7 Page - AMIC Technology

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