A25GFO080QL datasheet(19/58 Pages) AMICC

19 / 58 page

A25LQ080 Series

(April, 2016, Version 1.0)

AMIC Technology Corp.

Read Data Bytes at Higher Speed (FAST_READ)

The device is first selected by driving Chip Select ( S ) Low.

The instruction code for the Read Data Bytes at Higher

Speed (FAST_READ) instruction is followed by a 3-byte

address (A23-A0) and a dummy byte, each bit being

latched-in during the rising edge of Serial Clock (C). Then the

memory contents, at that address, is shifted out on Serial

Data Output (DO), each bit being shifted out, at a maximum

frequency fC, during the falling edge of Serial Clock (C).

The instruction sequence is shown in Figure 8. The first byte

addressed can be at any location. The address is

automatically incremented to the next higher address after

each byte of data is shifted out. The whole memory can,

therefore, be read with a single Read Data Bytes at Higher

Speed (FAST_READ) instruction. When the highest address

is reached, the address counter rolls over to 000000h,

allowing the read sequence to be continued indefinitely.

The Read Data Bytes at Higher Speed (FAST_READ)

instruction is terminated by driving Chip Select ( S ) High.

Chip Select ( S ) can be driven High at any time during data

output. Any Read Data Bytes at Higher Speed (FAST_READ)

instruction, while an Erase, Program or Write cycle is in

progress, is rejected without having any effects on the cycle

that is in progress.

Figure 8. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out Sequence

Instruction (0Bh)

High Impedance

MSB

810

01 2 3 4 5 6 7

24-Bit Address

28 29 30 31

23 22 21

3 21 0

Data Out 1

Data Out 2

32 33 34 35 36 37 38 39

65 4

40 41 42 43 44 45 46 47

Dummy Byte

MSB

7 6 54 32 1

MSB

7 6 54 32 1 0

Note: Address bits A23 to A20 are Don’t Care, for A25LQ080.

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