A25GFO080QL datasheet(24/58 Pages) AMICC

24 / 58 page

A25LQ080 Series

(April, 2016, Version 1.0)

AMIC Technology Corp.

Read OTP (ROTP)

The device is first selected by driving Chip Select ( S ) Low.

The instruction code for the Read OTP (ROTP) instruction is

followed by a 3-byte address (A23- A0) and a dummy byte.

Each bit is latched in on the rising edge of Serial Clock (C).

Then the memory contents at that address are shifted out on

Serial Data output (DO).

Each bit is shifted out at the maximum frequency, fC(Max.) on

the falling edge of Serial Clock (C).

The instruction sequence is shown in Figure 13.

The address is automatically incremented to the next higher

address after each byte of data is shifted out. When the

highest address is reached, the address counter rolls over to

000000h, allowing the read sequence to be continued

indefinitely.

The Read OTP (ROTP) instruction is terminated by driving

Chip Select ( S ) High. Chip Select ( S ) can be driven High at

any time during data output. Any Read OTP (ROTP)

instruction issued while an Erase, Program or Write Status

effect on the cycle that is in progress.

Figure 13. Read OTP (ROTP) instruction and data-out sequence

Instruction

(4Bh or 48h)

High Impedance

MSB

810

0 1 234 5 6 7

24-Bit Address

28 29 30 31

23 22 21

3 21 0

32 33 34 35 36 37 38 39

654

40 41 42 43 44 45 46 47

Dummy Byte

MSB

7 6 54 32 1

MSB

7 6 54 32 1 0

Data Out 1

Data Out n

Note: A23 to A6 are don’t care. (1

≤ n ≤ 64)

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