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DS1963S Datasheet(PDF) 14 Page - Dallas Semiconductor |
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DS1963S Datasheet(HTML) 14 Page - Dallas Semiconductor |
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14 / 37 page ![]() DS1963S 14 of 37 Memory and SHA Function Flow Chart (continued) Figure 7 AAh Read Scratch- pad ? HIDE = 1 ? Y N Y Offset = 11111b ? N Master TX Reset ? increments DS1963S SP. Offset Y N TA1 (T7:T0),TA2 (T15:T8) Bus Master RX and E/S Byte pad Offset = (T4:T0) DS1963S sets Scratch- S Scratchpad Offset Bus Master RX Data Byte from Bus Master RX FFh Byte Master TX Reset ? N Y Bus Master RX "1"s C3h Erase Scratch- Pad ? Bus Master TX TA1(T7:T0), TA2(T15:T8) Y N AUTH = 0 CHLG = 0 Erase Finished ? N Bus Master RX "1"s DS1963S fills the whole scratchpad with FFh bytes R Y DS1963S TX "0" DS1963S TX "1" Master TX Reset ? Master TX Reset ? N N Y Y From Figure 7 2nd part Spare Vertical From Figure 7 4th part To Figure 7 4th part To Figure 7 2nd part Y N HIDE = 0 of Command, Address, E/S Bus Master RX CRC16 Byte and data (HIDE = 0) or FFh (HIDE = 1) starting at the Scratchpad Offset |
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