DS1963S

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Note 1: The device provides functions to authenticate the host based on a system-wide secret, the

device’s ROM Registration number and a user-selected pin number that is installed in one of the

memory pages of a roaming data carrier.

Note 2: To find out whether a slave device is authentic the host writes a 3-byte “challenge” to the

scratchpad before issuing a command to compute the SHA-1 MAC over the challenge, the data

of a memory page, the page number, the page’s write-cycle counter, the device’s ROM

Registration number, and the secret associated with that page. By varying the challenge every

time it reads from a slave, the host can verify that the slave contains the correct secret and can

perform the required SHA computation in the required time.

Note 3: Manipulated data can be discovered if the data in the slave device is “signed” by an authorized

host. Signing consists of calculating a 160-bit SHA-1 MAC over the data to be protected, the

write-cycle counter of the page on which it is to be stored, the ROM ID of the slave device in

which it is to be stored, and any dedicated secret known only to authorized hosts. The MAC is

stored together with the application data (a monetary value together with a transaction ID code,

for example) in an appropriate memory page. To verify the authenticity of the data the host

repeats the process of signing. Any change in the data, the cycle counter, data carrier or an

invalid (not belonging to the system) signing-secret will make the verification of the signature

fail.

OVERVIEW

The block diagram in Figure 1 shows the relationships between the major control and memory sections of

the DS1963S. The DS1963S has six main data components: 1) 64-bit lasered ROM, 2) 256-bit scratch-

pad, 3) eight 32-byte pages of general-purpose SRAM, 4) eight 32-byte pages of SRAM protected by

write-cycle counters, 5) two 32-byte pages storing eight 64-bit secrets with individual write-cycle

counters, and 6) a 512-bit SHA-1 Engine (SHA = Secure Hash Algorithm). The hierarchical structure of

the 1-Wire protocol is shown in Figure 2. All write-cycle counters are 32 bits long and will not roll over

once the maximum count has been reached. The contents of the counters is read together with the

memory data using a special command. The bus master must first provide one of the seven ROM

Function Commands, 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, 5) Resume

Communication, 6) Overdrive-Skip ROM or 7) Overdrive-Match ROM. Upon completion of an

Overdrive ROM command byte executed at standard speed, the device will enter Overdrive mode where

all subsequent communication occurs at a higher speed. The protocol required for these ROM function

commands is described in Figure 10. After a ROM function command is successfully executed, the

memory functions become accessible and the master may provide any one of the eight memory function

commands. The protocol for these memory function commands is described in Figure 7. All data is read

and written least significant bit first.

PARASITE POWER

The block diagram (Figure 1) shows the parasite-powered circuitry. This circuitry “steals” energy

whenever the data contact is in the logic-high state. This stolen energy will provide sufficient power

while the data contact is in a logic-low state as long as the specified timing and voltage requirements are

met. The advantages of parasite power are two-fold: 1) by stealing energy off this input, the DS1963S-

internal lithium reserves are conserved and 2) if the lithium is exhausted for any reason, the ROM may

still be read normally. The remaining circuitry of the DS1963S is solely operated by lithium energy.