DS1963S datasheet(30/37 Pages) DALLAS

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DS1963S

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correct ROM and memory function command. In a mixed population network, the reset low time tRSTL

needs to be long enough for the slowest 1-Wire slave device to recognize it as a reset pulse. This duration

is 480µs at standard speed and 48µs at Overdrive speed. If the bus master uses slew-rate control on the

falling edge, it must pull down the line for tRSTL + tF to compensate for the edge. A tRSTL duration of

480µs or longer will exit the Overdrive Mode returning the device to standard speed. If the DS1963S is in

Overdrive Mode and tRSTL is no longer than 80µs, the device will remain in Overdrive Mode.

After the bus master has released the line it goes into receive mode (RX). Now, the 1-Wire bus is pulled

to VPUP via the pullup resistor or, in case of a DS2480B driver, by active circuitry. When the threshold

VTH is crossed, the DS1963S waits for tPDH and then transmits a Presence Pulse by pulling the line low for

tPDL. To detect a presence pulse, the master must test the logical state of the 1-Wire line at tMSP.

The tRSTH window must be at least the sum of tPDHMAX, tPDLMAX, and tRECMIN. Immediately after tRSTH is

expired, the DS1963S is ready for data communication. In a mixed population network, tRSTH should be

extended to minimum 480µs at standard speed and 48µs at Overdrive speed to accommodate other 1-

Wire devices.

INITIALIZATION PROCEDURE (RESET AND PRESENCE PULSES) Figure 11

RESISTOR

MASTER

DS1963S

tRSTL

tPDL

tRSTH

tPDH

MASTER TX RESET PULSE

MASTER RX PRESENCE PULSE

VPUP

VIHMASTER

VTH

VTL

VILMAX

tREC

tMSP

Read/Write Time Slots

Data communication with the DS1963S takes place in time slots that carry a single bit each. Write time

slots transport data from bus master to slave. Read time-slots transfer data from slave to master. The

definitions of the write and read time slots are illustrated in Figure 12.

All communication begins with the master pulling the data line low. As the voltage on the 1-Wire line

falls below the threshold VTL, the DS1963S starts its internal timing generator that determines when the

data line will be sampled during a write time slot and how long data will be valid during a read time slot.

Master to Slave

For a write-one time slot, the voltage on the data line must have crossed the VTHMAX threshold after the

write-one low time tW1LMAX is expired. For a write-zero time slot, the voltage on the data line must stay

below the VTHMIN threshold until the write-zero low time tW0LMIN is expired. For most reliable

communication the voltage on the data line should not exceed VILMAX during the entire tW0L window.

After the VTHMAX threshold has been crossed, the DS1963S needs a recovery time tREC before it is ready

for the next time slot.

DS1963S Datasheet(PDF) 30 Page - Dallas Semiconductor

DS1963S Datasheet(HTML) 30 Page - Dallas Semiconductor

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