STV3550 datasheet(67/144 Pages) STMICROELECTRONICS

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CPU and System Management Functional Description

STV3550

67/144

The ROM device may be easily replaced by a Flash or a Synchronous Flash (SFlash) device, but

the STV3550 is not able to support bursted accesses because there is no dedicated clock pad for a

SFlash device. Therefore, a Synchronous Flash device may be connected, but it will be used in

standard asynchronous mode by the STV3550.

The maximum ROM size is 16 MBits (or 2 MBytes), as the device is connected on 20 address lines

and 16 data lines.

Typical Flash devices, such as STM-29W160DT (STMicroelectronics) or AM29BL162C (AMD) are

compliant with the STV3550 Memory Interface.

The RAM device should be a Synchronous DRAM (SDRAM). A dedicated clock pad is available on

the STV3550. The maximum memory size is 256 MBits (or 32 MBytes), connected on 14 address

lines and 16 or 32 data lines. The SDRAM clock frequency may be up to 100 MHz.

Typical SDRAM devices, such as

µPD4564163 (NEC) or KM432S2030C (SAMSUNG) are

compliant with the STV3550 Memory Interface.

Memory devices can be connected in different ways to accommodate a large number of

applications.

6.3.2

Configuring the STV3550 Memory Interface during Boot

The STV3550 always boots on the ROM device, regardless of the SDRAM configuration. After

reset, the STV3550 Memory Interface accesses the ROM at a very low speed in order to

accommodate the slowest ROM devices available on the memory market.

Note:

The STV3550 boot address is 0x7FFFFFFF in the Flash memory.

Since the STV3550 is able to accommodate several memory configurations, the STV3550 Memory

Interface should be configured accordingly during the boot. Software is used to configure the

memory (i.e. SDRAM size, data bus size, SDRAM and ROM latencies, etc.) and does not require

the use of external pins.

STV3550 embeds an internal RAM that can be used during the boot until the external SDRAM is

ready.

Once the STV3550 Memory Interface has been programmed properly, it is strongly recommended

not to apply any further modifications.

6.3.3

Address Format

When interfacing a memory device through the STV3550 Memory Interface, the STV3550 uses a

word address. Depending on the data bus size of the device, and knowing that the minimum data

bus size is 16 bits:

●

When using a 16-bit data word device (1 word = 2 bytes), bit 0 is the least significant address

bit,

●

When using a 32-bit data word device (1 word = 4 bytes), bit 1 is the least significant address

bit.

Byte Enable lines (NOT_BEx signals) are provided for processing only parts of data words when

required.

Note:

For SDRAM, the address bus is multiplexed on 14 address lines (row, column and bank addresses),

while Flash devices do not use multiplexed addresses.

6.3.4

Control Registers

The STV3550 Memory Interface is able to support various memory configurations by programming

control registers.

STV3550 Datasheet(PDF) 67 Page - STMicroelectronics

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