STV3550 datasheet(76/144 Pages) STMICROELECTRONICS

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STV3550

CPU and System Management Functional Description

However, the STV3550 Memory Interface provides control over the SDRAM clock in order to switch

the I/O without any timing violations according to Low Power Mode entry and exit specified for the

SDRAM devices.

6.3.11 Memory Configurations

In all the following configurations, the Flash device has always 16 data lines and no more than 20

address lines.

The Flash device does not receive any clock signals from the STV3550, and the STV3550

considers the Flash memory as an asynchronous device.

The SDRAM device always receives clock signals from the STV3550.

The Address bus is always shared between the SDRAM and Flash memories. Additional memory

parameters can be adjusted through software (SDRAM size and organization, Flash latency, etc.).

6.3.11.1 Low-Cost Configuration

This configuration requires a SDRAM device with 16 data lines. A typical SDRAM size may be 64

Mbits (8 MBytes).

The Flash data bus is separate from the SDRAM data bus. Therefore, constraints when placing the

devices are reduced, i.e. wires are short and wire loads are small.

Since 16-bit data words are used, address outputs ADDR[11:0] are connected to the SDRAM

address bus and address outputs ADDR[16:15] are used as Bank Activate signals.

Flash is a Read-only device.

6.3.11.2 High-End Configuration with one SDRAM Device

This configuration requires a SDRAM with 32 data lines. A typical size of the SDRAM may be 128

Mbits (16 MBytes).

Figure 48: Low-Cost Configuration

ADDR[19:0]

DATA[15:0]

A[11:0]

DQ[15:0]

RAS

CAS

FLASH

16Mb

DQM[1:0]

SDRAM

64Mb

STV3550

NOT_CS_FLASH

ADDR[19:0]

FLASH_D[15:0]

NOT_RAS

NOT_CAS

RD_NOT_WR

NOT_BE[1:0]

CKOUT_SDRAM

SDRAM_D[15:0]

NOT_CS_SDRAM

[19:0]

[11:0]

[15:0]

[19:0]

CLK

BA[1:0]

[16:15]

CKEN

CKIN_SDRAM

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