STV3550 datasheet(24/144 Pages) STMICROELECTRONICS

No. de pieza	STV3550

Descripción Electrónicos	LCD and Matrix Display TV Processor

PDF	144 Pages

Scroll/Zoom	100%

Fabricante Electrónico	STMICROELECTRONICS [STMicroelectronics]

Página de inicio	http://www.st.com

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STV3550

3.3

Video Display Pipeline

The Video Display block includes all the processing required for adapting the incoming video

stream to the selected display format. Depending on the up-conversion mode, this block generates

the correct video sequence with the selected number of pixels per line, lines per field or fields per

second. It uses high-resolution horizontal and vertical polyphase filters to interpolate the additional

pixels and lines required for the selected display format. These filters are also used for zoom-in and

zoom-out rescaling.

It also includes picture improvement algorithms (PSI/CTI) to provide the picture with a more “high-

resolution” aspect.

Figure 8: Video Display Flowchart

Pixel FIFO

All data is in Analog Y/Cr/Cb format

Pixel Clock Domain

VTG

V-rst

Display Clock Domain

STBus Interconnect

T2 Memory Interface

4:2:2 to 4:4:4 Up-Conversion

Line Buffer

CTI

PSI

HFC/VFC

Luma Path

HFC/VFC

Chroma Path

Pan/Scan

System Clock

Domain

STV3550 Datasheet(PDF) 24 Page - STMicroelectronics