STV3550 datasheet(68/144 Pages) STMICROELECTRONICS

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STV3550

CPU and System Management Functional Description

All the control registers are implemented in the STV3550 Memory Interface and are accessible by

the ST20.

6.3.5

Memory Configurations

The STV3550 Memory Interface is able to support 2 hardware configurations depending on

bandwidth requirements and application constraints:

●

two separate 16-bit data word buses for Flash and SDRAM devices (low-cost STV3550

applications)

●

a single merged 32-bit data word bus shared by all memory devices for high bandwidth

requirements (high-end STV3550 applications)

The STV3550 Memory Interface has an address translator that is helpful when designing a single

board embedding both low-cost and high-end configurations without modifying the SDRAM address

bus connection on the printed circuit board.

6.3.6

Clock Management and Timing Issues

The STV3550 Memory Interface provides clock management features to:

●

control the polarity of the clock signal sent to the SDRAM

●

choose the SDRAM clock between the internal clock or a locked clock signal generated by a

Delay Locked Line (DLL)

●

provide low power control on SDRAM devices

The STV3550 Memory Interface and SDRAM operate at the same frequency (100 MHz at Full

Speed).

When operating at frequencies greater than 70 MHz, the DLL must be used to ensure the safe data

exchange between the STV3550 Memory Interface and the SDRAM device. The SDRAM clock is

included within a loop in order to better take into account the propagation time in the wires between

the STV3550 and SDRAM devices.

In order to accommodate various wire configurations, the SDRAM clock loop can be internally or

externally closed to the STV3550. When externally closed, a dedicated Clock Input pad is used.

When interfacing the STV3550 with high-speed memory devices such as SDRAM, the user may

face timing issues such as setup- and hold-time violations.The STV3550 Memory Interface is also

able to eliminate these timing problems by providing written data, strobes and addresses either on

the falling or rising edge of SDRAM clock signals.

6.3.7

STV3550 Memory Interfaces

The memory interface of the STV3550 is built around 61 lines. Certain lines have single functions,

while others support several functions depending on the memory configuration. By sharing

functions, the number of required pins is reduced, since the STV3550 is not able to access both

Flash and SDRAM devices at the same time.

Pins have been named according to their function when used in a low-cost application

configuration. There are no application-specific pins for a given memory configuration. Applications

STV3550 Datasheet(PDF) 68 Page - STMicroelectronics

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