STV3550 datasheet(75/144 Pages) STMICROELECTRONICS

No. de pieza	STV3550

Descripción Electrónicos	LCD and Matrix Display TV Processor

PDF	144 Pages

Scroll/Zoom	100%

Fabricante Electrónico	STMICROELECTRONICS [STMicroelectronics]

Página de inicio	http://www.st.com

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CPU and System Management Functional Description

STV3550

75/144

6.3.10 SDRAM Low Power Mode

The STV3550 is able to set the SDRAM into Low Power mode. Most SDRAM devices have a Clock

Enable input pin that internally gates the SDRAM clock supplied by the STV3550.

The STV3550 does not have the corresponding output pin included in its memory interface, but this

feature can be emulated using any of the standard STV3550 I/Os.

Figure 46: Typical Read Access Cycle (CAS Latency = 2)

Figure 47: Typical Refresh Access Cycle

NOT_RAS

NOT_CAS

RD_NOT_WR

NOT_BE[1:0]

SDRAM_D[15:0]

RAS to CAS

PrechargeTime

ADDR[16:15],

Row

Column

Row

Read

activate

CKOUT_SDRAM

NOT_CS_SDRAM

Column

CAS Latency =2

Precharge

All

AP=1

NOP

BusReleaseTime

ADDR[11:0]

(ADDR[19:18])

(FLASH_D[15:0])

DQM high to data out

forced to High-Z

equals to 2 clock

cycles (fixed

NOT_BE latency for

reads).

NOT_RAS

RD_NOT_WR

RefreshTime

NOT_CS_SDRAM

CKOUT_SDRAM

PrechargeTime

NOT_CAS

1 cycle

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