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STV3550 Datasheet(PDF) 127 Page - STMicroelectronics |
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STV3550 Datasheet(HTML) 127 Page - STMicroelectronics |
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127 / 144 page ![]() STV3550 127/144 7.9.3 Register There is not a dedicated register interface (STBus T1), only a single ‘I_IRDA_ON’ primary input with a reset value of ‘0’. When the IrDA block is ‘off’ (bit equal to ‘0’), the block is bypassed. ● O_TXD = ‘0’ ● O_UARTF_RXD = ‘1’ Note: The dedicated register bit is in the VTG block. Figure 77: IrDA Encoding Scheme Figure 78: IrDA Decoding Scheme 16 x Clock CLK_SYS I_UARTF_TXD O_TXD 16 x Clock 16 cycles I_UARTF_TXD O_TXD 16 x Clock 16 cycles 7 cycles 3 cycles 16 x Clock CLK_SYS O_UARTF_RXD I_RXD 16 x Clock 16 cycles 3 cycles 16 cycles |
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