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SL28610 Datasheet(PDF) 5 Page - Silicon Laboratories

No. de pieza SL28610
Descripción Electrónicos  Low Power Clock Generator for Intel짰 Ultra Mobile Platform
PDF  23 Pages
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Fabricante Electrónico  SILABS [Silicon Laboratories]
Página de inicio  http://www.silabs.com
Logo SILABS - Silicon Laboratories

SL28610 Datasheet(HTML) 5 Page - Silicon Laboratories

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SL28610
........................ DOC #: SP-AP-0078 (Rev. 1.0) Page 5 of 23
Control Registers
Byte 0: Control Register 0
Bit
@Pup
Name
Description
7
1
PLL1_EN
PLL1 Enable
0 = Disabled, 1 = Enabled
6
1
PLL2_EN
PLL2 Enable
0 = Disabled, 1 = Enabled
5
1
PLL3_EN
PLL3 Enable
0 = Disabled, 1 = Enabled
4
0
RESERVED
RESERVED
3
1
CPU_DIV
CPU Output Divider Enable
0 = Disabled, 1 = Enabled
2
1
PCIe_DIV
PCIe Output Divider Enable
0 = Disabled, 1 = Enabled
1
1
LCD_DIV
LCD Output Divider Enable
0 = Disabled, 1 = Enabled
0
1
DOT96_DIV
DOT96 Output Divider Enable
0 = Disabled, 1 = Enabled
Byte 1: Control Register 1
Bit
@Pup
Name
Description
7
1
PLL1_Spread _EN
PLL1 Spread Enable
0 = Disabled, 1 = Enabled
6
1
PLL3_Spread _EN
PLL3 Spread Enable
0 = Disabled, 1 = Enabled
5
0
PLL3_CFB2
PLL3 Spread Spectrum Select
PLL3_CFB[2:0]
000 = -%0.5 (Down Spread) - Default
001 = -%1.0, DS
010 = -%1.5, DS
011 = -% 2.0, DS
100 = %+0.30 (Center Spread)
101 = %+0.50, CS
110 = %+1.00, CS
111 = %+1.25, CS
4
0
PLL3_CFB1
3
0
PLL3_CFB0
2
0
RESERVED
RESERVED
1
0
RESERVED
RESERVED
0
0
RESERVED
RESERVED
Byte 2: Control Register 2
Bit
@Pup
Name
Description
7
1
CPU0_OE
Output enable for CPU0
0 = Output Disabled, 1 = Output Enabled
6
1
CPU1_OE
Output enable for CPU1
0 = Output Disabled, 1 = Output Enabled
5
1
CPU2_OE
Output enable for CPU2
0 = Output Disabled, 1 = Output Enabled
4
1
PCIe0_OE
Output enable for PCIe0
0 = Output Disabled, 1 = Output Enabled
3
1
PCIe1_OE
Output enable for PCIe1
0 = Output Disabled, 1 = Output Enabled



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