SL28610 datasheet(11/23 Pages) SILABS

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SL28610

...................... DOC #: SP-AP-0078 (Rev. 1.0) Page 11 of 23

Byte 20: Control Register 20

Byte 21: Control Register 21

CKPWRGD#/PD (Power down) Clarification

The CKPWRGD#/PD pin is a dual-function pin. During initial

power

up,

the

functions

CKPWRGD#.

Once

CKPWRGD# has been sampled HIGH by the clock chip, the

pin assumes PD functionality. The PD pin is an asynchronous

active HIGH input used to shut off all clocks cleanly before

shutting off power to the device. This signal is synchronized

internally to the device before powering down the clock

synthesizer. PD is also an asynchronous input for powering up

the system. When PD is asserted HIGH, clocks are driven to

a LOW value and held before turning off the VCOs and the

crystal oscillator.

CKPWRGD#/PD (Power down) Assertion

When PD is sampled HIGH by two consecutive rising edges

of CPUC, all single-ended outputs will be held HIGH on their

next HIGH-to-LOW transition and differential clocks must held

HIGH. When PD mode is desired as the initial power on state,

PD must be asserted HIGH in less than 10

s after asserting

CKPWRGD.

CKPWRGD#/PD (Power Down) Deassertion

The power up latency is less than 1.8 ms. This is the time from

the deassertion of the PD pin or the ramping of the power

supply until the time that stable clocks are generated from the

clock chip. All differential outputs stopped in a three-state

condition, resulting from power down are driven high in less

than 300

s of PD deassertion to a voltage greater than

200 mV. After the clock chip’s internal PLL is powered up and

locked, all outputs are enabled within a few clock cycles of

each clock. Figure 2 is an example showing the relationship of

clocks coming up.

Bit

@Pup

Name

Description

PLL3_DAF_N7

If Prog_PLL3_EN is set, the values programmed in PLL3_DAF_N[7:0] and

PLL3_DAF_M[7:0] are used to determine the PLL3 output frequency.

PLL3_DAF_N6

PLL3_DAF_N5

PLL3_DAF_N4

PLL3_DAF_N3

PLL3_DAF_N2

PLL3_DAF_N1

PLL3_DAF_N0

Bit

@Pup

Name

Description

PLL3_DAF_M7

If Prog_PLL3_EN is set, the values programmed in PLL3_DAF_N[7:0] and

PLL3_DAF_M[7:0] are used to determine the PLL3 output frequency.

PLL3_DAF_M6

PLL3_DAF_M5

PLL3_DAF_M4

PLL3_DAF_M3

PLL3_DAF_M2

PLL3_DAF_M1

PLL3_DAF_M0

SL28610 Datasheet(PDF) 11 Page - Silicon Laboratories

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