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SL28610 Datasheet(PDF) 10 Page - Silicon Laboratories

No. de pieza SL28610
Descripción Electrónicos  Low Power Clock Generator for Intel짰 Ultra Mobile Platform
PDF  23 Pages
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Fabricante Electrónico  SILABS [Silicon Laboratories]
Página de inicio  http://www.silabs.com
Logo SILABS - Silicon Laboratories

SL28610 Datasheet(HTML) 10 Page - Silicon Laboratories

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SL28610
...................... DOC #: SP-AP-0078 (Rev. 1.0) Page 10 of 23
Byte 17: Control Register 17
Byte 18: Control Register 18
Byte 19: Control Register 19
Bit
@Pup
Name
Description
7
0
PLL1_DAF_N7
If Prog_PLL1_EN is set, the values programmed in PLL1_DAF_N[7:0] and
PLL1_DAF_M[7:0] are used to determine the PLL1 output frequency.
6
0
PLL1_DAF_N6
5
0
PLL1_DAF_N5
4
0
PLL1_DAF_N4
7
0
PLL1_DAF_N3
2
0
PLL1_DAF_N2
1
0
PLL1_DAF_N1
0
0
PLL1_DAF_N0
Bit
@Pup
Name
Description
7
0
PLL1_DAF_M7
If Prog_PLL1_EN is set, the values programmed in PLL1_DAF_N[7:0] and
PLL1_DAF_M[7:0] are used to determine the PLL1 output frequency.
6
0
PLL1_DAF_M6
5
0
PLL1_DAF_M5
4
0
PLL1_DAF_M4
7
0
PLL1_DAF_M3
2
0
PLL1_DAF_M2
1
0
PLL1_DAF_M1
0
0
PLL1_DAF_M0
Bit
@Pup
Name
Description
7
0
RESERVED
RESERVED
6
0
RESERVED
RESERVED
5
0
Prog_PLL1_EN
Programmable PLL1 frequency enable
0 = Disabled, 1= Enabled
4
0
Prog_PLL3_EN
Programmable PLL3 frequency enable
0 = Disabled, 1= Enabled
3
0
CPU_OEB_DRIVE _Mode Controls CPU Output Drive States
1 = OUT=LOW and OUT#=LOW
0= OUT=HIGH and OUT#=LOW
2
0
PCIe_OEB_DRIVE _Mode Controls PCIe Output Drive States
1 = OUT=LOW and OUT#=LOW
0= OUT=HIGH and OUT#=LOW
1
0
LVDS_OEB_DRIVE _Mode Controls LVDS Output Drive States
1 = OUT=LOW and OUT#=LOW
0= OUT=HIGH and OUT#=LOW
0
0
DOT_OEB_DRIVE _Mode Controls DOT Output Drive States
1 = OUT=LOW and OUT#=LOW
0= OUT=HIGH and OUT#=LOW



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