LSM6DSR datasheet(47/168 Pages) STMICROELECTRONICS

47 / 168 page

9.9

FIFO_CTRL4 (0Ah)

FIFO control register 4 (r/w)

Table 37. FIFO_CTRL4 register

DEC_TS_

BATCH_1

DEC_TS_

BATCH_0

ODR_T_

BATCH_1

ODR_T_

BATCH_0

0(1)

FIFO_

MODE2

FIFO_

MODE1

FIFO_

MODE0

1. This bit must be set to '0' for the correct operation of the device.

Table 38. FIFO_CTRL4 register description

DEC_TS_BATCH_[1:0]

Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL

and GYRO BDR divided by decimation decoder.

(00: Timestamp not batched in FIFO (default);

01: Decimation 1: max(BDR_XL[Hz],BDR_GY[Hz]) [Hz];

10: Decimation 8: max(BDR_XL[Hz],BDR_GY[Hz])/8 [Hz];

11: Decimation 32: max(BDR_XL[Hz],BDR_GY[Hz])/32 [Hz])

ODR_T_BATCH_[1:0]

Selects batch data rate (write frequency in FIFO) for temperature data

(00: Temperature not batched in FIFO (default);

01: 1.6 Hz;

10: 12.5 Hz;

11: 52 Hz)

FIFO_MODE[2:0]

FIFO mode selection

(000: Bypass mode: FIFO disabled;

001: FIFO mode: stops collecting data when FIFO is full;

010: Reserved;

011: Continuous-to-FIFO mode: Continuous mode until trigger is deasserted, then FIFO mode;

100: Bypass-to-Continuous mode: Bypass mode until trigger is deasserted, then Continuous mode;

101: Reserved;

110: Continuous mode: if the FIFO is full, the new sample overwrites the older one;

111: Bypass-to-FIFO mode: Bypass mode until trigger is deasserted, then FIFO mode.)

LSM6DSR

FIFO_CTRL4 (0Ah)

DS11976 - Rev 2

page 47/168

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