AD9381SLASHPCB datasheet(29/44 Pages) AD

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AD9381

Rev. 0 | Page 29 of 44

0x2E—Bit[7] Ctrl Enable

When set, this bit allows Ctrl [3:0] signals decoded from the

DVI to be output on the I2S data pins. 0 = I2S signals on I2S

lines. 1 = Ctrl [3:0] output on I2S lines. The power-up default

setting is 0.

0x2E—Bits[6:5] I2S Output Mode

These bits select between four options for the I2S output: I2S,

right-justified, left-justified, or raw IEC60958 mode. The

power-up default setting is 00.

Table 15. I2S Output Select

I2S Output Mode

Result

I2S mode

Right-justified

Left-justified

Raw IEC60958 mode

0x2E—Bits[4:0] I2S Bit Width

These bits set the I2S bit width for right-justified mode. The

power-up default setting is 24 bits.

0x2F—Bit[6] TMDS Sync Detect

This read-only bit indicates the presence of a TMDS DE.

0 = no TMDS DE present. 1 = TMDS DE detected.

0x2F—Bit[5] TMDS Active

This read-only bit indicates the presence of a TMDS clock.

0 = no TMDS clock present. 1 = TMDS clock detected.

0x2F—Bit[4] AV Mute

This read-only bit indicates the presence of AV mute based on

general control packets. 0 = AV not muted. 1 = AV muted.

0x2F—Bit[3] HDCP Keys Read

This read-only bit reports if the HDCP keys were read

successfully. 0 = failure to read HDCP keys. 1 = HDCP keys

read.

0x2F—Bits[2:0] HDMI Quality

These read-only bits indicate a level of HDMI quality based on

the DE (display enable) edges. A larger number indicates a

higher quality.

0x30—Bit[6] HDMI Content Encrypted

This read-only bit is high when HDCP decryption is in use

(content is protected). The signal goes low when HDCP is not

being used. Customers can use this bit to determine whether or

not to allow copying of the content. The bit should be sampled

at regular intervals since it can change on a frame by frame

basis. 0 = HDCP not in use. 1 = HDCP decryption in use.

0x30—Bit[5] DVI HSYNC Polarity

This read-only bit indicates the polarity of the DVI HSYNC.

0 = DVI HSYNC polarity is low active. 1 = DVI HSYNC

polarity is high active.

0x30—Bit[4] DVI VSYNC Polarity

This read-only bit indicates the polarity of the DVI VSYNC.

0 = DVI VSYNC polarity is low active. 1 = DVI VSYNC polarity

is high active.

0x30—Bits[3:0] HDMI Pixel Repetition

These read-only bits indicate the pixel repetition on DVI. 0 =

1×, 1 = 2×, 2 = 3×, up to a maximum repetition of 10× (0x9).

Table 16.

Select

Repetition Multiplier

0000

1×

0001

2×

0010

3×

0011

4×

0100

5×

0101

6×

0110

7×

0111

8×

1000

9×

1001

10×

MACROVISION

0x31—Bits[7:4] Macrovision Pulse Max

These bits set the pseudo sync pulse width maximum for

Macrovision detection in pixel clocks. This is functional for

13.5 MHz SDTV or 27 MHz progressive scan. Power-up

default is 9.

0x31—Bits[3:0] Macrovision Pulse Min

These bits set the pseudo sync pulse width maximum for

Macrovision detection in pixel clocks. This is functional for

13.5 MHz SDTV or 27 MHz progressive scan. Power-up

default is 6.

0x32—Bit[7] Macrovision Oversample Enable

Tells the Macrovision detection engine whether oversampling is

used. This accommodates 27 MHz sampling for SDTV and 54

MHz sampling for progressive scan and is used as a correction

factor for clock counts. Power-up default is 0.

0x32—Bit[6] Macrovision PAL Enable

Tells the Macrovision detection engine to enter PAL mode when

set to 1. Default is 0 for NTSC mode.

0x32—Bits[5:0] Macrovision Line Count Start

Set the start line for Macrovision detection. Along with

pulses are expected to occur. The power-up default is Line 13.

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