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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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AD9381/PCB Datasheet(PDF) 18 Page - Analog Devices |
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AD9381/PCB Datasheet(HTML) 18 Page - Analog Devices |
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18 / 44 page  AD9381 Rev. 0 | Page 18 of 44 Hex Address Read/Write or Read Only Bits Default Value Register Name Description 0x43 Read/Write [4:0] ***00010 CSC_Coeff_B4 MSB MSB, Register 0x44. 0x44 Read/Write [7:0] 10010010 CSC_Coeff_B4 LSB CSC coefficient for equation: ROUT = (A1 × RIN) + (A2 × GIN) + (A3 × BIN) + A4 GOUT = (B1 × RIN) + (B2 × GIN) + (B3 × BIN) + B4 BOUT = (C1 × RIN) + (C2 × GIN) + (C3 × BIN) + C4 0x45 Read/Write [4:0] ***00000 CSC_Coeff_C1 MSB MSB, Register 0x46. 0x46 Read/Write [7:0] 00000000 CSC_Coeff_C1 LSB CSC coefficient for equation: ROUT = (A1 × RIN) + (A2 × GIN) + (A3 × BIN) + A4 GOUT = (B1 × RIN) + (B2 × GIN) + (B3 × BIN) + B4 BOUT = (C1 × RIN) + (C2 × GIN) + (C3 × BIN) + C4 0x47 Read/Write [4:0] ***01000 CSC_Coeff_C2 MSB MSB, Register 0x48. 0x48 Read/Write [7:0] 00000000 CSC_Coeff_C2 LSB CSC coefficient for equation: ROUT = (A1 × RIN) + (A2 × GIN) + (A3 × BIN) + A4 GOUT = (B1 × RIN) + (B2 × GIN) + (B3 × BIN) + B4 BOUT = (C1 × RIN) + (C2 × GIN) + (C3 × BIN) + C4 0x49 Read/Write [4:0] ***01110 CSC_Coeff_C3 MSB MSB, Register 0x4A. 0x4A Read/Write [7:0] 10000111 CSC_Coeff_C3 LSB CSC coefficient for equation: ROUT = (A1 × RIN) + (A2 × GIN) + (A3 × BIN) + A4 GOUT = (B1 × RIN) + (B2 × GIN) + (B3 × BIN) + B4 BOUT = (C1 × RIN) + (C2 × GIN) + (C3 × BIN) + C4 0x4B Read/Write [4:0] ***11000 CSC_Coeff_C4 MSB MSB, Register 0x4C. 0x4C Read/Write [7:0] 10111101 CSC_Coeff_C4 LSB CSC coefficient for equation: ROUT = (A1 × RIN) + (A2 × GIN) + (A3 × BIN) + A4 GOUT = (B1 × RIN) + (B2 × GIN) + (B3 × BIN) + B4 BOUT = (C1 × RIN) + (C2 × GIN) + (C3 × BIN) + C4 0x50 Read/Write [7:0] 00100000 Test Must be written to 0x20 for proper operation. 0x56 Read/Write [7:0] 00001111 Test Must be written to default of 0x0F for proper operation. 0x57 Read/Write [7] 0******* A/V Mute Override A1 overrides the AV mute value with Bit 6. [6] *0****** AV Mute Value Sets AV mute value if override is enabled. [3] ****0*** Disable Video Mute Disables mute of video during AV mute. [2] *****0** Disable Audio Mute Disables mute of audio during AV mute. 0x58 Read/Write [7] MCLK PLL Enable MCLK PLL enable—uses analog PLL. [6:4] MCLK PLL_N MCLK PLL N [2:0]—this controls the division of the MCLK out of the PLL: 0 = /1, 1 = /2, 2 = /3, 3 = /4, etc. [3] N_CTS_Disable Prevents the N/CTS packet on the link from writing to the N and CTS registers. [2:0] MCLK FS_N Controls the multiple of 128 Fs, used for MCLK out . 0 = 128 fS, 1 = 256 fS, 2 = 384, 7 = 1024 fS. 0x59 Read/Write [6] MDA/MCL PU This disables the MDA/MCL pull-ups. [5] CLK Term O/R Clock termination power-down override: 0 = auto, 1 = manual. [4] Manual CLK Term Clock termination: 0 = normal, 1 = disconnected. [2] FIFO Reset UF This bit resets the audio FIFO if underflow is detected. [1] FIFO Reset OF This bit resets the audio FIFO if overflow is detected. [0] MDA/MCL Three-State This bit three-states the MDA/MCL lines. |
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