AD9381SLASHPCB datasheet(12/44 Pages) AD

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AD9381

Rev. 0 | Page 12 of 44

AUDIO PLL SETUP

Data contained in the audio infoframes, among other registers,

define for the AD9381 HDMI receiver not only the type of

audio, but the sampling frequency (fS). The audio infoframe also

contains information about the N and CTS values used to

recreate the clock. With this information it is possible to

regenerate the audio sampling frequency. The audio clock is

regenerated by dividing the 20-bit CTS value into the TMDS

clock, then multiplying by the 20-bit N value. This yields a

multiple of the fs (sampling frequency) of either 128 × fs or

256 × fs. It is possible for this to be specified up to 1024 × fs.

SINK DEVICE

SOURCE DEVICE

1N AND CTS VALUES ARE TRANSMITTED USING THE

AUDIO CLOCK REGENERATION PACKET. VIDEO

CLOCK IS TRANSMITTED ON TMDS CLOCK CHANNEL.

128 ×

VIDEO

CLOCK

128 ×

TMDS

CLOCK

CTS1

DIVIDE

CYCLE

TIME

COUNTER

DIVIDE

CTS

MULTIPLY

Figure 7. N and CTS for Audio Clock

In order to provide the most flexibility in configuring the audio

sampling clock, an additional PLL is employed. The PLL

characteristics are determined by the loop filter design, the PLL

charge pump current, and the VCO range setting. The loop

filter design is shown in Figure 8.

8nF

80nF

1.5k

FILT

PVD

Figure 8. PLL Loop Filter Detail

To fully support all audio modes for all video resolutions up to

1080p, it is necessary to adjust certain audio-related registers

from their power-on default values. Table 9 describes these

registers and gives their recommended settings.

Table 9. AD9398 Audio Register Settings

Bits

Recommended

Setting

Function

Comments

0x01

7:0

0x00

PLL Divisor (MSBs)

0x02

7:4

0x40

PLL Divisor (Lab’s)

7:6

VCO Range

5:3

010

Charge Pump Current

The analog video PLL is also used for the audio clock

circuit when in HDMI mode. This is done automatically.

0x03

PLL Enable

In HDMI mode, this bit enables a lower frequency to be

used for audio MCLK generation.

0x34

Audio Frequency Mode Override

Allows the chip to determine the low frequency mode

of the audio PLL.

PLL Enable

This enables the analog PLL to be used for audio MCLK

generation.

6:4

011

MCLK PLL Divisor

When the analog PLL is enabled for MCLK generation,

another frequency divider is provided. These bits set

the divisor to 4.

N/CTS Disable

The N and CTS values should always be enabled.

0x58

2:0

0**

MCLK Sampling Frequency

000 = 128 × fS

001 = 256 × fS

010 = 384 × fS

011 = 512 × fS

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