AD9381SLASHPCB datasheet(7/44 Pages) AD

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AD9381

Rev. 0 | Page 7 of 44

Pin Type

Pin No.

Mnemonic

Function

Value

REFERENCES

FILT

Connection for External Filter Components for Audio PLL

PVDD

POWER SUPPLY

80, 76, 72, 67,

45, 33

Analog Power Supply and DVI Terminators

3.3 V

100, 90, 10

VDD

Output Power Supply

1.8 V to 3.3 V

59, 56, 54

PVDD

PLL Power Supply

1.8 V

48, 32, 30

DVDD

Digital Logic Power Supply

1.8 V

GND

Ground

0 V

CONTROL

SDA

Serial Port Data I/O

3.3 V CMOS

SCL

Serial Port Data Clock

3.3 V CMOS

HDCP

DDCSCL

HDCP Slave Serial Port Data Clock

3.3 V CMOS

DDCSDA

HDCP Slave Serial Port Data I/O

3.3 V CMOS

PU2

This should be pulled up to 3.3 V through a 10 kΩ resistor

3.3 V CMOS

PU1

This should be pulled up to 3.3 V through a 10 kΩ resistor

3.3 V CMOS

AUDIO DATA OUTPUTS

S/PDIF

S/PDIF Digital Audio Output

VDD

I2S0

I2S Audio (Channel 1, Channel 2)

VDD

I2S1

I2S Audio (Channels 3, Channel 4)

VDD

I2S2

I2S Audio (Channels 5, Channel 6)

VDD

I2S3

I2S Audio (Channels 7, Channel 8)

VDD

MCLKIN

External Reference Audio Clock In

VDD

MCLKOUT

Audio Master Clock Output

VDD

SCLK

Audio Serial Clock Output

VDD

LRCLK

Data Output Clock for Left and Right Audio Channels

VDD

DATA ENABLE

Data Enable

3.3 V CMOS

RTERM

Sets Internal Termination Resistance

500 Ω

Table 6. Pin Function Descriptions

Mnemonic

Description

INPUTS

Rx0+

Digital Input Channel 0 True.

Rx0−

Digital Input Channel 0 Complement.

Rx1+

Digital Input Channel 1 True.

Rx1−

Digital Input Channel 1 Complement.

Rx2+

Digital Input Channel 2 True.

Rx2−

Digital Input Channel 2 Complement.

These six pins receive three pairs of transition minimized differential signaling (TMDS) pixel data (at 10× the pixel

rate) from a digital graphics transmitter.

RxC+

Digital Data Clock True.

RxC−

Digital Data Clock Complement.

This clock pair receives a TMDS clock at 1× pixel data rate.

FILT

External Filter Connection.

For proper operation, the audio clock generator PLL requires an external filter. Connect the filter shown in

Figure 8 to this pin. For optimal performance, minimize noise and parasitics on this node. For more information

see the PCB Layout Recommendations section .

PWRDN

Power-Down Control/Three-State Control.

The function of this pin is programmable via Register 0x26 [2:1].

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