AD9381SLASHPCB datasheet(15/44 Pages) AD

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AD9381

Rev. 0 | Page 15 of 44

Hex

Address

Read/Write

or Read Only

Bits

Default Value

Description

[4]

***1****

Field Output Polarity

Output field polarity.

0 = active low out.

1 = active high out.

[0]

*******0

Output CLK Invert

0 = don’t invert clock out.

1 = invert clock out.

0x25

Read/Write

[7:6]

01******

Output CLK Select

Selects which clock to use on output pin. 1× CLK is

divided down from TMDS clock input when pixel

repetition is in use.

00 = ½× CLK.

01 = 1× CLK.

10 = 2× CLK.

11 = 90° phase 1× CLK.

[5:4]

**11****

Output Drive Strength

Sets the drive strength of the outputs.

00 = lowest, 11 = highest.

[3:2]

****00**

Output Mode

Selects the data output mapping.

00 = 4:4:4 mode (normal).

01 = 4:2:2 + DDR 4:2:2 on blue.

10 = DDR 4:4:4 + DDR 4:2:2 on blue.

11 = 12-bit 4:2:2 (HDMI option only).

[1]

******1*

Primary Output Enable

Enables primary output.

[0]

*******0

Secondary Output

Enable

Enables secondary output (DDR 4:2:2 in Output

Mode 1 and Mode 2).

0x26

Read/Write

[7]

0*******

Output Three-State

Three-state the outputs.

[5]

**0*****

SPDIF Three-State

Three-state the S/PDIF output.

[4]

***0****

I2S Three-State

Three-state the I2S output and the MCLK out.

[3]

****1***

Power-Down Pin Polarity

Sets polarity of power-down pin.

0 = active low.

1 = active high.

[2:1]

*****00*

Power-Down Pin

Function

Selects the function of the power-down pin.

00 = power-down.

01 = power-down and three-state SOG.

10 = three-state outputs only.

11 = three-state outputs and SOG.

[0]

*******0

Power-Down

0 = normal.

1 = power-down.

0x27

Read/Write

[7]

1*******

Auto Power-Down

Enable

0 = disable auto low power state.

1 = enable auto low power state.

[6]

*0******

HDCP A0

Sets the LSB of the address of the HDCP I2C.

Set to 1 only for a second receiver in a dual-link

configuration.

0 = use internally generated MCLK.

1 = use external MCLK input.

[5]

**0*****

MCLK External Enable

If an external MCLK is used, it must be locked to the

video clock according to the CTS and N available in

the I2C. Any mismatch between the internal MCLK

and the input MCLK results in dropped or repeated

audio samples.

[4]

***0****

BT656 EN

Enables EAV/SAV codes to be inserted into the

video output data.

[3]

****0***

Force DE Generation

Allows use of the internal DE generator in DVI

mode.

AD9381/PCB Datasheet(PDF) 15 Page - Analog Devices

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