AD9381

Rev. 0 | Page 14 of 44

2-WIRE SERIAL REGISTER MAP

The AD9381 is initialized and controlled by a set of registers that determines the operating modes. An external controller is employed to

write and read the control registers through the 2-wire serial interface port.

Table 11. Control Register Map

Hex

Address

Read/Write

or Read Only

Bits

Default Value

Register Name

Description

0x00

Read

[7:0]

00000000

Chip Revision

Chip revision ID. Revision is read [7:4]. [3:0].

0x01

Read/Write

[7:0]

01101001

PLL Divider MSB

PLL feedback divider value MSB.

0x02

Read/Write

[7:4]

1101****

PLL Divider

PLL feedback divider value.

0x03

Read/Write

[7:6]

01******

VCO Range

VCO range.

[5:3]

**001***

Charge Pump

Charge pump current control for PLL.

[2]

*****0**

PLL Enable

This bit enables a lower frequency to be used for

audio MCLK generation

0x11

Read/Write

[7]

0*******

HSYNC Source

0 = HSYNC.

1 = SOG.

[6]

*0******

HSYNC Source Override

0 = auto HSYNC source.

1 = manual HSYNC source.

[5]

**0*****

VSYNC Source

0 = VSYNC.

1 = VSYNC from SOG.

[4]

***0****

VSYNC Source Override

0 = auto HSYNC source.

1 = manual HSYNC source.

[3]

****0***

Channel Select

0 = Channel 0.

1 = Channel 1.

[2]

*****0**

Channel Select Override

0 = autochannel select.

1 = manual channel select.

[1]

******0*

Interface Select

0 = analog interface.

1 = digital interface.

[0]

*******0

Interface Override

0 = auto-interface select.

1 = manual interface select.

0x12

Read/Write

[7]

1*******

Input HSYNC Polarity

0 = active low.

1 = active high.

[6]

*0******

HSYNC Polarity Override

0 = auto HSYNC polarity.

1 = manual HSYNC polarity.

[5]

**1*****

Input VSYNC Polarity

0 = active low.

1 = active high.

[4]

***0****

VSYNC Polarity Override

0 = auto VSYNC polarity.

1 = manual VSYNC polarity.

0x17

Read

[3:0]

****0000

HSYNCs Per VSYNC MSB

MSB of HSYNCs per VSYNC.

0x18

Read

[7:0]

00000000

HSYNCs Per VSYNC

HSYNCs per VSYNC count.

0x22

Read/Write

[7:0]

4

VSYNC Duration

VSYNC duration.

0x23

Read/Write

[7:0]

32

HSYNC Duration

HSYNC duration. Sets the duration of the output

HSYNC in pixel clocks.

0x24

Read/Write

[7]

1*******

HSYNC Output Polarity

Output HSYNC polarity.

0 = active low out.

1 = active high out.

[6]

*1******

VSYNC Output Polarity

Output VSYNC polarity.

0 = active low out.

1 = active high out.

[5]

**1*****

DE Output Polarity

Output DE polarity.

0 = active low out.

1 = active high out.