CC1021-RTR1 datasheet(31/92 Pages) TI

31 / 92 page

CC1021

SWRS045

Page 31 of 91

ChBW > SBW + 2 · f_error

The DEC_DIV[2:0] bits in the FILTER

bandwidth. The 6 dB bandwidth is given

by:

ChBW = 307.2 / (DEC_DIV + 1) [kHz]

where the IF frequency is set to 307.2

kHz. Table 18 shows the available channel

filter bandwidths.

There is a tradeoff between selectivity as

well as sensitivity and accepted frequency

tolerance. In applications where larger

frequency drift is expected, the filter

bandwidth can be increased, but with

reduced adjacent channel rejection (ACR)

and sensitivity.

Filter bandwidth

[kHz]

FILTER.DEC_DIV[2:0]

[decimal(binary)]

38.4

7 (111b)

43.9

6 (110b)

51.2

5 (101b)

61.4

4 (100b)

76.8

3 (011b)

102.4

2 (010b)

153.6

1 (001b)

307.2

0 (000b)

Table 18. Channel filter bandwidth

12.3. Demodulator, Bit Synchronizer and Data Decision

The block diagram for the demodulator,

data slicer and bit synchronizer is shown

in Figure 13. The built-in bit synchronizer

synchronizes the internal clock to the

incoming

data

and

performs

data

decoding. The data decision is done using

over-sampling and digital filtering of the

incoming signal. This improves the

reliability of the data transmission. Using

the synchronous modes simplifies the

data-decoding task substantially.

The

recommended

preamble

ë010101Ö í bit pattern. The same bit

pattern should also be used in Manchester

mode, giving a ë011001100110Ö ëchipí

pattern. This is necessary for the bit

synchronizer to synchronize to the coding

correctly.

The data slicer does the bit decision.

Ideally the two received FSK frequencies

are placed symmetrically around the IF

frequency. However, if there is some

frequency error between the transmitter

and the receiver, the bit decision level

should be adjusted accordingly. In CC1021

this is done automatically by measuring

the two frequencies and use the average

value as the decision level.

The digital data slicer in CC1021 uses an

average value of the minimum and

maximum frequency deviation detected as

the comparison level. The RXDEV_X[1:0]

and

RXDEV_M[3:0]

the

AFC_CONTROL register are used to set

the expected deviation of the incoming

signal. Once a shift in the received

frequency larger than the expected

deviation is detected, a bit transition is

recorded and the average value to be

used by the data slicer is calculated.

The minimum number of transitions

required to calculate a slicing level is 3.

That is, a 010 bit pattern (NRZ).

The actual number of bits used for the

averaging can be increased for better data

decision accuracy. This is controlled by

the

SETTLING[1:0]

bits

the

AFC_CONTROL register. If RX data is

present in the channel when the RX chain

is turned on, then the data slicing estimate

will usually give correct results after 3 bit

transitions. The data slicing accuracy will

increase after this, depending on the

SETTLING[1:0] bits. If the start of

transmission occurs after the RX chain

has turned on, the minimum number of bit

transitions (or preamble bits) before

correct data slicing will depend on the

SETTLING[1:0] bits.

The automatic data slicer average value

function can be disabled by setting

SETTLING[1:0] = 00. In this case a

symmetrical

signal

around

the

frequency is assumed.

The internally calculated average FSK

frequency value gives a measure for the

frequency offset of the receiver compared

CC1021-RTR1 Datasheet(PDF) 31 Page - Texas Instruments

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