ADS6445 datasheet(13/75 Pages) STMICROELECTRONICS

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TIMING SPECIFICATIONS

(1)

ADS6445, ADS6444

ADS6443, ADS6442

SLAS531 – MAY 2007

Typical values are at 25

°C, min and max values are across the full temperature range T

MIN = –40°C to TMAX = 85°C, AVDD =

LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 V

PP clock amplitude, CL = 5 pF

(2), I

O = 3.5

mA, R

L = 100 Ω

(3), no internal termination, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Aperture jitter

All

Uncertainty in the sampling instant

250

fs rms

INTERFACE: 2-wire, DDR bit clock, 14x serialization

ADS6445

0.35

0.55

ADS6444

0.45

0.65

tsu

Data setup time(4)(5)(6)

From data cross-over to bit clock cross-over

ADS6443

0.65

0.85

ADS6442

0.8

1.1

ADS6445

0.35

0.58

ADS6444

0.5

0.7

Data hold time(4)(5)(6)

From bit clock cross-over to data cross-over

ADS6443

0.7

0.9

ADS6442

0.8

1.1

Input clock rising edge cross-over to frame clock rising edge

tpd_clk

Clock propagation delay (6)

All

3.4

4.4

5.4

cross-over

Bit clock cycle-cycle jitter (5)

All

350

ps pp

Frame clock cycle-cycle jitter (5)

All

ps pp

Below specifications apply for 5 MSPS

≤ Fs ≤ 125 MSPS and all interface options.

Aperture delay

All

Delay from input clock rising edge to the actual sampling instant

Aperture delay variation

All

Channel-channel within same device

–250

±80

250

Clock

ADC Latency (7)

All

Time for a sample to propagate to ADC outputs, see Figure 1

cycles

Time to valid data after coming out of global power down

100

µs

Time to valid data after input clock is re-started

100

µs

Wake up time

All

Clock

Time to valid data after coming out of channel standby

200

cycles

tRISE

Data rise time

All

From –100 mV to +100 mV

100

200

tFALL

Data fall time

All

From +100 mV to –100 mV

100

200

Bit clock and frame clock rise

tRISE

All

From –100mV to +100mV

100

200

time

Bit clock and frame clock fall

tFALL

All

From +100mV to –100mV

100

200

time

LVDS Bit clock duty cycle

All

45%

50%

55%

LVDS Frame clock duty cycle

All

47%

50%

53%

(1)

Timing parameters are ensured by design and characterization and not tested in production.

(2)

CL is the external single-ended load capacitance between each output pin and ground.

(3)

Io refers to the LVDS buffer current setting; RL is the external differential load resistance between the LVDS output pair.

(4)

Timing parameters are measured at the end of a 2 inch pcb trace (100-

Ω characteristic impedance) terminated by R

Land CL.

(5)

Setup and hold time specifications take into account the effect of jitter on the output data and clock.

(6)

Refer to Output Timings in application section for timings at lower sampling frequencies and other interface options.

(7)

Note that the total latency = ADC latency + internal serializer latency. The serializer latency depends on the interface option selected as

shown in Table 27.

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