ADS6445 datasheet(17/75 Pages) STMICROELECTRONICS

17 / 75 page

www.ti.com

DESCRIPTION OF PARALLEL PINS

ADS6445, ADS6444

ADS6443, ADS6442

SLAS531 – MAY 2007

Table 5. SCLK, SDATA Control Pins

SCLK

SDATA

DESCRIPTION

LOW

NORMAL conversion.

SYNC – ADC outputs sync pattern on all channels. This pattern can be used by the receiver to align the

LOW

HIGH

deserialized data to the frame boundary. See Capture Test Patterns for details.

POWER DOWN – Global power down, all channels of the ADC are powered down, including internal references,

HIGH

LOW

PLL and output buffers.

DESKEW – ADC outputs deskew pattern on all channels. This pattern can be used by the receiver to ensure

HIGH

deserializer uses the right clock edge. See Capture Test Patterns for details.

Table 6. SEN Control Pin

SEN

DESCRIPTION

External reference and 0 dB coarse gain (full-scale = 2 VPP)

(3/8)LVDD

External reference and 3.5 dB coarse gain (full-scale = 1.34 VPP)

(5/8)LVDD

Internal reference and 3.5 dB coarse gain (full-scale = 1.34 VPP)

LVDD

Internal reference and 0 dB coarse gain (full-scale = 2 VPP)

Independent of the programming mode used, after power-up the parallel pins PDN, CFG1 to CFG4 will

automatically configure the device as per the voltage applied (refer to Table 7 to Table 11).

Table 7. PDN Control Pin

PDN

DESCRIPTION

Normal operation

AVDD

Power down global

Table 8. CFG1 Control Pin

CFG1

DESCRIPTION

DDR Bit clock and 1-wire interface

(3/8)LVDD

Not used

(5/8)LVDD

SDR Bit clock and 2-wire interface

LVDD

DDR Bit clock and 2-wire interface

Table 9. CFG2 Control Pin

CFG2

DESCRIPTION

14x Serialization and capture at falling edge of bit clock (only in 2-wire SDR bit clock mode)

(3/8)LVDD

16x Serialization and capture at falling edge of bit clock (only in 2-wire SDR bit clock mode)

(5/8)LVDD

16x Serialization and capture at rising edge of bit clock (only in 2-wire SDR bit clock mode)

LVDD

14x Serialization and capture at rising edge of bit clock (only in 2-wire SDR bit clock mode)

Table 10. CFG3 Control Pin

CFG3

RESERVED - TIE TO GROUND

Table 11. CFG4 Control Pin

CFG4

DESCRIPTION

MSB First and 2s complement

(3/8)LVDD

MSB First and offset binary

(5/8)LVDD

LSB First and offset binary

LVDD

LSB First and 2s complement

Submit Documentation Feedback

ADS6445 Datasheet(PDF) 17 Page - STMicroelectronics

ADS6445 Datasheet(HTML) 17 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75

Datasheet Descarga

Enlace URL