ADS6445 datasheet(46/75 Pages) STMICROELECTRONICS

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APPLICATION INFORMATION

THEORY OF OPERATION

ANALOG INPUT

INP

INM

25 W

RCR Filter

50 W

3.2 pF

1pF

par2

1pF

par2

6nH

pkg

6nH

pkg

2pF

bond

2pF

bond

200

esr

200

esr

0.8 pF

par1

Sampling

Switch

Sampling

Switch

Sampling

Capacitor

Sampling

Capacitor

4.0 pF

samp

4.0 pF

samp

S0237-01

ADS6445, ADS6444

ADS6443, ADS6442

SLAS531 – MAY 2007

The ADS6445/ADS6444/ADS6443/ADS6442 (ADS644X) is a family of quad channel, 14-bit pipeline ADC based

on switched capacitor architecture in CMOS technology.

The conversion is initiated simultaneously by all the four channels at the rising edge of the external input clock.

After the input signals are captured by the sample and hold circuit of each channel, the samples are sequentially

converted by a series of low resolution stages. The stage outputs are combined in a digital correction logic block

to form the final 14-bit word with a latency of 12 clock cycles. The 14-bit word of each channel is serialized and

output as LVDS levels. In addition to the data streams, a bit clock and frame clock are also output. The frame

clock is aligned with the 14-bit word boundary.

The analog input consists of a switched-capacitor based differential sample and hold architecture, shown in

Figure 82. This differential topology results in very good AC performance even for high input frequencies. The

INP and INM pins have to be externally biased around a common-mode voltage of 1.5 V, available on VCM pin

13. For a full-scale differential input, each input pin INP, INM has to swing symmetrically between VCM + 0.5 V

and VCM – 0.5 V, resulting in a 2-VPP differential input swing. The maximum swing is determined by the internal

reference voltages REFP (2.0 V nominal) and REFM (1.0 V, nominal). The sampling circuit has a 3 dB

bandwidth that extends up to 500 MHz (see Figure 83, shown by the transfer function from the analog input pins

to the voltage across the sampling capacitors, TF_ADC).

Figure 82. Input Sampling Circuit

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