ELANSC310 datasheet(41/119 Pages) AMD

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Élan™SC310 Microcontroller Data Sheet

PREL IMINARY

SRAM

When using SRAM instead of DRAM for main memory,

up to 16 Mbyte can be accessed, the SRAM being or-

ganized as one or two banks. Each bank is 16 bits wide

and is provided with a low and high byte select.

An SRAM memory interface is selected by setting bit 0

of the Miscellaneous 6 Register, Index 70h. If this is

done, CAS1H, CAS1L, CAS0H, and CAS0L will have

their alternate function as SRAM chip select pins 3–0

(SRCS3–SRCS0). Table 17 shows the key SRAM ac-

cess pins.

See Table 14 on page 39 for bank size settings.

The MS2–MS0 bits in the Memory Configuration Reg-

ister, Index 66h, are also used to program the total

SRAM size. Bit 7 of Index Register B4h must be

cleared for SRAM configurations. Table contains infor-

mation about SRAM wait state logic, and Table 28 on

page 61 contains SRAM interface alternate pin infor-

mation.

The PMU Modes and Clock Generators

The Power Management Unit (PMU) monitors all sys-

tem activities (e.g., keyboard, screen, and disk events),

and, based on the state of the system, determines in

which operating mode the system should be running.

The PMU supports six operating modes, each defined

by a different combination of CPU and peripheral oper-

ation, as shown in the list that follows.

1. High-Speed PLL. All clocks are at their fastest

speed and all peripherals are powered up. This is

the mode the system enters when activity is de-

tected by the PMU.

2. Low-Speed PLL. The internal CPU clock is re-

duced to a maximum of 4.608 MHz. All other clocks

and peripherals operate at full speed. This is the

first level of power conservation; it is entered after a

specified elapsed time with no activity.

3. Doze. The second level of power conservation. The

CPU, system, and DMA clocks are stopped. The

high-speed PLL is turned off. This mode is entered

after a specified elapsed time with no activity.

4. Sleep. Additional clocks and peripherals are

stopped after additional inactivity has been de-

tected. The exact parameters can be programmed.

The Low-Speed PLL can be left on, so a quick star-

tup is possible.

5. Suspend. Virtually all of the system is shut down,

including all clocks, the 8254 timer, and the Phase

Locked Loops (a programmable recovery time is

associated with this mode). The 32.768 kHz clock

input is still running.

6. Off. This level is virtually the same as Suspend

mode. Two outputs can be programmed to change

state when the transition from Suspend mode to Off

mode occurs. DRAM refresh can be disabled in

OFF mode.

In addition, the ÉlanSC310 microcontroller can man-

age the power consumption of peripheral devices. This

control can be forced upon entering a specific operat-

ing mode or it can be handled directly by firmware. The

ÉlanSC310 microcontroller PMU controls five power

Table 17.

SRAM Access Pins

Pin Name

I/O

Function

SRCS0

SRAM Bank 0 Low Byte Select

SRCS1

SRAM Bank 0 High Byte Select

SRCS2

SRAM Bank 1 Low Byte Select

SRCS3

SRAM Bank 1 High Byte Select

SA23–SA1

Address (16-Mbyte maximum)

MWE

Write enable

Table 18.

SRAM Wait State Select Logic

Configuration

Number of Wait States

SRAM Speed

Index 63h

Bit 4

Index 66h

Bits 1 and 0

Read

Write

20 MHz

25 MHz

33 MHz

0 0

45ns

35ns

25ns

0 1

80ns

55ns

35ns

0 1

120 ns

100 ns

70 ns

Notes:

Refer to Index 70h, bit 0, in the ÉlanTMSC310 Microcontroller Programmer’s Reference Manual, order #20665 for information

on how to select SRAM versus DRAM.

ELANSC310 Datasheet(PDF) 41 Page - Advanced Micro Devices

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