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ELANSC310 Datasheet(PDF) 1 Page - Advanced Micro Devices |
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ELANSC310 Datasheet(HTML) 1 Page - Advanced Micro Devices |
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1 / 119 page  PRELIMINARY This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this product without notice. Publication# 20668 Rev: B Amendment/0 Issue Date: October 1997 Élan™SC310 Single-Chip, 32-Bit, PC/AT Microcontroller DISTINCTIVE CHARACTERISTICS n Highly integrated, single-chip CPU and system logic – Optimized for embedded PC applications – Combines 32 bit, x86 compatible, low-voltage CPU with memory controller, PC/AT peripheral controllers, real-time clock, and PLL clock generators – 0.7 micron, low-voltage, CMOS process, fully static n Enhanced Am386®SXLV CPU core – 25 MHz or 33 MHz operating frequencies – 3.3 V core, 3.3 V or 5 V memory and I/O – Low-power, fully static design for long battery life – System Management Mode (SMM) for power management control n Integrated power management functions – Internal clock generators (using multiple Phase- Locked Loops and one external 32-KHz crystal) – Supports CPU System Management Mode (SMM) – Multiple operating modes: High Speed PLL, Low Speed PLL, Doze, Sleep, Suspend, and Off. Fully static design allows stopped clock. – Comprehensive control of system and peripheral clocks – Five external power management control pins – Suspend refresh of DRAM array – Clock switching during ISA cycles – Low power consumption: 0.12 mW typical Suspend mode power – Simultaneous multiple-voltage I/O pads operate at either 3.3 V or 5 V. Core operates at 3.3 V for minimum power consumption. n Integrated memory controller – Controls symmetrically addressable DRAM or asymmetrical 512 Kbyte x 8 bit or 1 Mbyte x 16 bit DRAM or SRAM as main memory – Zero wait-state access with 70 ns, Page mode DRAMs – Supports up to 16 Mbyte system memory – Supports up to 16 Mbyte of application ROM/ Flash, and 320 Kbyte direct ROM BIOS access. Also supports shadow RAM – Fully PC/AT compatible n Integrated PC/AT-lompatible leripheral logic – One programmable interval timer (fully 8254 compatible) – Two programmable interrupt controllers (8259A compatible) – Two DMA controllers (8237A compatible) – Built-in real-time clock (146818A compatible), with an additional 114 bytes of RAM – Internal Phase-Locked Loops (PLL) generate all clocks from single 32.768 kHz crystal input n Bus configurations – 16-bit data path – Optional bus configurations: — 386 Local Bus mode with subset ISA — Maximum ISA Bus mode – Four programmable chip selects – Built-in 8042 chip select n Serial port controller (16450 UART compatible) n Bidirectional parallel port (EPP compliant) |
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