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ELANSC310 Datasheet(PDF) 94 Page - Advanced Micro Devices |
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ELANSC310 Datasheet(HTML) 94 Page - Advanced Micro Devices |
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94 / 119 page  94 Élan™SC310 Microcontroller Data Sheet PREL IMINARY Table 47. DRAM First Cycle Read Access (See Figure 38) Notes: For more information about DRAM first cycle read wait states, see the DRAM First Cycle Wait State Select Logic table in Chapter 4 of the ÉlanTMSC310 Microcontroller Programmer’s Reference Manual, order #20665. Symbol Parameter Description Wait States Min Max Unit t5a CAS Low to data valid (read access time) 120 ns 250 ns 380 ns t28a RAS Low to data valid (read access time) 150 ns 280 ns 3 110 ns t30 MA valid setup to RAS Low N/A 0 ns t31 MA hold from RAS Low N/A 10 ns t32 MA setup to CAS Low N/A 0 ns t33 RAS hold from CAS Low N/A 20 ns t34 RAS precharge from CAS High N/A 10 ns t38 MA hold from CAS active N/A 15 ns t39 RAS to CAS delay N/A 20 ns t40 RAS pulse width N/A 70 10,000 ns t41a CAS pulse width (read, first cycle) 130 ns 260 ns 390 ns t44a CAS hold from RAS Low 160 ns 290 ns 3 120 ns Table 48. DRAM Bank/Page Miss Read Cycles (See Figure 38) Symbol Parameter Description Wait State Min Max Unit t5b CAS Low to data valid (read access time) 335 ns 465 ns 580 ns t28b RAS Low to data valid (read access time) 365 ns 495 ns 5 110 ns t29a CAS precharge (page miss read) N/A 30 ns t33 RAS hold from CAS Low N/A 20 ns t34 RAS precharge from CAS High N/A 10 ns t36 RAS precharge (page miss) 338 ns 438 ns 553 ns t39 RAS to CAS delay N/A 20 ns t40 RAS pulse width N/A 70 10,000 ns t41b CAS pulse width (read, page miss) 345 ns 475 ns 590 ns |
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