ELANSC310 datasheet(8/119 Pages) AMD

8 / 119 page

PREL IMINARY

Élan™SC310 Microcontroller Data Sheet

LIST OF FIGURES

Figure 1.

PLL Block Diagram .................................................................................................. 42

Figure 2.

Clock Steering Block Diagram ................................................................................. 43

Figure 3.

Typical System Design with Secondary Power Supply to Maintain RTC When

Primary Power Supply is Off (DRAM Refresh is Optional.)...................................... 47

Figure 4.

ÉlanSC310 Microcontroller I/O Structure ................................................................. 48

Figure 5.

ÉlanSC310 Microcontroller Unidirectional Parallel Port Data Bus Implementation... 52

Figure 6.

The ÉlanSC310 Microcontroller Bidirectional Parallel Port

and EPP Implementation ......................................................................................... 53

Figure 7.

Typical System Block Diagram (Maximum ISA Mode)............................................. 55

Figure 8.

Bus Option Configuration Select .............................................................................. 59

Figure 9.

3.3-V I/O Drive Type E Rise Time............................................................................ 74

Figure 10. 3.3-V I/O Drive Type E Fall Time ............................................................................. 74

Figure 11. 5-V I/O Drive Type E Rise Time............................................................................... 75

Figure 12. 5-V I/O Drive Type E Fall Time ................................................................................ 75

Figure 13. 3.3-V I/O Drive Type D Rise Time............................................................................ 76

Figure 14. 3.3-V I/O Drive Type D Fall Time ............................................................................. 76

Figure 15. 5-V I/O Drive Type D Rise Time............................................................................... 77

Figure 16. 5-V I/O Drive Type D Fall Time ................................................................................ 77

Figure 17. 3.3-V I/O Drive Type C Rise Time............................................................................ 78

Figure 18. 3.3-V I/O Drive Type C Fall Time ............................................................................. 78

Figure 19. 5-V I/O Drive Type C Rise Time............................................................................... 79

Figure 20. 5-V I/O Drive Type C Fall Time ................................................................................ 79

Figure 21. 3.3-V I/O Drive Type B Rise Time............................................................................ 80

Figure 22. 3.3-V I/O Drive Type B Fall Time ............................................................................. 80

Figure 23. 5-V I/O Drive Type B Rise Time............................................................................... 81

Figure 24. 5-V I/O Drive Type B Fall Time ................................................................................ 81

Figure 25. 3.3-V I/O Drive Type A Rise Time............................................................................ 82

Figure 26. 3.3-V I/O Drive Type A Fall Time ............................................................................. 82

Figure 27. 5-V I/O Drive Type A Rise Time............................................................................... 83

Figure 28. 5-V I/O Drive Type A Fall Time ................................................................................ 83

Figure 29. X32 Oscillator Circuit................................................................................................ 85

Figure 30. Loop-Filter Component ............................................................................................ 86

Figure 31. Key to Switching Waveforms ................................................................................... 87

Figure 32. Power-Up Sequence Timing .................................................................................... 89

Figure 33. Micro Power Off Mode Exit ...................................................................................... 90

Figure 34. Entering Micro Power Off Mode (DRAM Refresh Disabled) .................................... 91

Figure 35. Entering Micro Power Off Mode (DRAM Refresh Enabled) ..................................... 91

Figure 36. DRAM Timings, Page Hit ......................................................................................... 93

Figure 37. DRAM Timings, Refresh Cycle ................................................................................ 93

Figure 38. DRAM First Cycle and Bank/Page Miss (Read Cycles)........................................... 95

Figure 39. DRAM First Cycle Bank/Page Miss (Write Cycles) .................................................. 97

Figure 40. Local Bus Interface .................................................................................................. 99

Figure 41. BIOS ROM Read/Write 8-Bit Cycle........................................................................ 101

Figure 42. DOS ROM Read/Write 8-Bit Cycle......................................................................... 103

Figure 43. DOS ROM Read/Write 16-Bit Cycle....................................................................... 105

Figure 44. ISA Memory Read/Write 8-Bit Cycle ...................................................................... 107

Figure 45. ISA Memory Read/Write 16-Bit Cycle .................................................................... 109

Figure 46. ISA Memory Read/Write 0 Wait State Cycle.......................................................... 111

Figure 47. ISA I/O 8-Bit Read/Write Cycle .............................................................................. 113

Figure 48. ISA I/O 16-Bit Read/Write Cycle ............................................................................ 115

Figure 49. EPP Data Register Write Cycle.............................................................................. 116

Figure 50. EPP Data Register Read Cycle ............................................................................. 117

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