DSP56303 datasheet(185/292 Pages) FREESCALE

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SCI Programming Model

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

8-17

8.6.3 SCI Clock Control Register (SCCR)

The SCCR is a read/write register that controls the selection of clock modes and baud rates for

the transmit and receive sections of the SCI interface. The SCCR is cleared by a hardware RESET

signal.

TCM

RCM

SCP

COD

CD11

CD10

CD9

CD8

54321

CD7

CD6

CD5

CD4

CD3

CD2

CD1

CD0

Reserved. Read as 0. Write to 0 for future compatibility.

Figure 8-4. SCI Clock Control Register (SCCR)

Table 8-5. SCI Clock Control Register (SCCR) Bit Definitions

Bit

Number

Bit Name

Reset

Value

Description

23–16

Reserved. Write to 0 for future compatibility.

TCM

Transmit Clock Source

Selects whether an internal or external clock is used for the transmitter. If TCM is cleared,

the internal clock is used. If TCM is set, the external clock (from the SCLK signal) is used.

RCM

Receive Clock Mode Source

Selects whether an internal or external clock is used for the receiver. If RCM is cleared, the

internal clock is used. If RCM is set, the external clock (from the SCLK signal) is used.

TCM

RCM

TX Clock

RX Clock

SCLK

Mode

Internal

Output

Synchronous/asynchronous

Internal

External

Input

Asynchronous only

External

Internal

Input

Asynchronous only

External

Input

Synchronous/asynchronous

SCP

Clock Prescaler

Selects a divide by 1 (SCP is cleared) or divide by 8 (SCP is set) prescaler for the clock

divider. The output of the prescaler is further divided by 2 to form the SCI clock.

COD

Clock Out Divider

The clock output divider is controlled by COD and the SCI mode. If the SCI mode is

synchronous, the output divider is fixed at divide by 2. If the SCI mode is asynchronous,

either:

• If COD is cleared and SCLK is an output (that is, TCM and RCM are both cleared), then

the SCI clock is divided by 16 before being output to the SCLK signal. Thus, the SCLK

output is a 1

× clock.

• If COD is set and SCLK is an output, the SCI clock is fed directly out to the SCLK signal.

Thus, the SCLK output is a 16

× baud clock.

11–0

CD[11–0]

Clock Divider

Specifies the divide ratio of the prescale divider in the SCI clock generator. A divide ratio

from 1 to 4096 (CD[11–0] = $000 to $FFF) can be selected.

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