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MP2886A Datasheet(PDF) 80 Page - Monolithic Power Systems |
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MP2886A Datasheet(HTML) 80 Page - Monolithic Power Systems |
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80 / 113 page ![]() MP2886A – DIGITAL PWM CONTROLLER WITH PMBUS AND PWM-VID MP2886A Rev. 1.0 www.MonolithicPower.com 80 1/21/2019 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2019 MPS. All Rights Reserved. MFR_PWMVID_FLTR_CTRL1 (B1h) This register sets the performance of the digital PWM-VID filters. Command MFR_PWMVID_FLTR_CTRL1 Format Unsigned binary Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w Function Bits Bit Name Description 15:13 DVID_DOWN_START_ THRE Threshold for the downward DVID starting indicator (DVID_TRIG_MODE = 0). When VOUT is settled, the controller uses the output of the second-stage filter as VO_REF. When the calculated VID_TARGET is less than the current VO_REF - DVID_DOWN_START_THRE, the controller enters the downward DVID, and VO_REF switches to the first-stage filter output. DVID_DOWN_START_THRE must be greater than DVID_DOWN_END_THRE. 12:10 DVID_UP_START_ THRE Threshold for the upward DVID starting indicator (DVID_TRIG_MODE = 0). When VOUT is settled, the controller uses the output of the second-stage filter as VO_REF. When the calculated VID_TARGET is greater than the current VO_REF + DVID_UP_START_THRE, the controller enters the upward DVID, and VO_REF switches to the output of the first-stage filter. DVID_UP_START_THRE must be greater than DVID_UP_END_THRE. 9:7 DVID_DOWN_END_ THRE Threshold for the downward DVID ending indicator. During the downward DVID, the controller uses the output of the first-stage filter as VO_REF. When the current VO_REF is less than the calculated VID_TARGET + DVID_DOWN_END_THRE, this bit switches to the output of the second-stage filter . DVID_DOWN_START_THRE must be greater than DVID_DOWN_END_THRE. 6:2 FILT2_CHECK_TIME Check time of the synchronizing function of the second-stage PWM-VID filter to improve output voltage accuracy after DVID. 100µs/LSB. The second-stage PWM-VID filter uses an internal hysteresis module to avoid jitter on its output. When the output remains unchanged during this checking time, the hysteresis module synchronizes its output with the input to eliminate small DC errors. 1:0 SECOND_FIL_AVE Averaging window of the second-stage PWM-VID filter. 00: average of 512 points 01: average of 1024 points 10: average of 2048 points 11: average of 4056 points |
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