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AD9553/PCBZ Datasheet(PDF) 32 Page - Analog Devices

No. de pieza AD9553/PCBZ
Descripción Electrónicos  Flexible Clock Translator for GPON, Base Station, SONET/SDH, T1/E1, and Ethernet
PDF  44 Pages
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

AD9553/PCBZ Datasheet(HTML) 32 Page - Analog Devices

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AD9553
Rev. 0 | Page 32 of 44
REGISTER MAP
A bit that labeled “aclr” is an active high, autoclearing bit. When set to a Logic 1 state, the control logic automatically returns it to a
Logic 0 state upon completion of the indicated task.
Table 27. Register Map
Addr.
(Hex)
Register
Name
(MSB)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(LSB)
Bit 0
Default
0x00
Serial port
control
0
LSB first
Soft reset
(aclr)
1
1
Soft reset
LSB first
0
0x18
0x04
Readback
control
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Readback
control
0x00
0x05
I/O update
Unused
Unused
Unused
Unused
Unused
Unused
Unused
I/O update
(aclr)
0x00
0x0A
PLL charge
pump and
PFD control
Charge pump current control[7:0]
(3.5 μA granularity, ~900 μA full scale)
0x80
0x0B
Enable SPI
control of
charge
pump
current
Enable SPI
control of
antiback-
lash
period
Charge pump
mode[1:0]
Disable
charge
pump
PFD
feedback
input edge
control
PFD
reference
input edge
control
Force VCO
to midpoint
frequency
0x30
0x0C
Unused
Unused
Unused
Unused
Unused
Charge pump clock div[2:0]
0x00
0x0D
Antibacklash control[1:0]
Unused
Unused
Unused
Unused
Unused
PLL lock
detector
power-
down
0x00
0x0E
VCO control
Calibrate
VCO (aclr)
Enable
ALC
ALC threshold[2:0]
Enable SPI
control of
VCO
calibration
Boost VCO
supply
Enable SPI
control of
VCO band
setting
0x70
0x0F
VCO level control[5:0]
Unused
Unused
0x80
0x10
VCO band control[6:0]
Unused
0x80
0x11
PLL and
output
frequency
control
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
0x00
0x12
Feedback divider (N)[19:12]
0x80
0x13
Feedback divider (N)[11:4]
0x00
0x14
Feedback divider (N) [3:0]
Enable SPI
control of
feedback
divider
Enable SPI
control of
output
dividers
Unused
Reset PLL
(aclr)
0x00
0x15
P1 divider[9:2]
0x20
0x16
P1 divider[1:0]
P2 divider[9:4]
0x00
0x17
P2 divider[3:0]
Enable test
port
Test mux[1:0]
Unused
0x01
0x18
0
P0 divider[1:0]
Unused
Unused
Unused
Unused
Unused
0x00
0x19
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
0x20
0x1A
Input
receiver and
band gap
control
Reference
reset (aclr)
Band gap voltage adjust[4:0]
(00000 = maximum, 11111 = minimum)
Unused
Enable SPI
control of
band gap
voltage
0x00
0x1B
XTAL
control
Disable SPI
control of
XTAL tuning
capacitance
0
XTAL tuning capacitor control[5:0]
(0.25 pF per bit, inverted binary coding)
0x80
0x1C
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
0x00
0x1D
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
0x00
0x1E
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused



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