AD9553SLASHPCBZ datasheet(10/44 Pages) AD

10 / 44 page

AD9553

Rev. 0 | Page 10 of 44

NOTES

1. EXPOSED DIE PAD MUST BE CONNECTED TO GND.

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

REFA

REFB/REFA

24 GND

23 OUT2

21 VDD

20 LOCKED

19 LDO

18 VDD

17 LDO

TOP VIEW

(Not to Scale)

AD9553

OUT2

Figure 2. Pin Configuration

Table 13. Pin Function Descriptions

Pin No.

Mnemonic

Type1

Description

29, 30, 31,

32, 1, 2

Y0, Y1, Y2, Y3,

Y4, Y5

Control Pins. These pins select one of 51 preset output frequency combinations for OUT1 and

OUT2. Note that when all six control pins are Logic 0, SPI programming is active.

3, 4, 5, 6

A0, A1, A2, A3

Control Pins. These pins select one of 15 preset input reference frequencies. Note that when all four

control pins are Logic 0, SPI programming is active.

REFA

Reference Clock Input. Connect this pin to a single-ended active clock input signal. Alternatively,

this pin is the noninverted part of a differential clock input signal.

REFB/REFA

Reference Clock Input. Connect this pin to a single-ended active clock input signal. Alternatively,

this pin is the inverted part of a differential clock input signal.

9, 10

XTAL

Crystal Resonator Input. Connect a crystal resonator across these pins. When using the preset

input/output frequencies via the Y[5:0] and A[3:0] pins, the crystal must have a resonant frequency

of 25 MHz with a specified load capacitance of 10 pF.

SEL REFB

Control Pin. This pin allows manual selection of REFA (Logic 0) or REFB (Logic 1) as the active

reference assuming that the desired reference signal is present. Note that this pin is nonfunctional

when Register 0x29[5] = 1.

OM2/CS

Digital Input. When the device is not in SPI mode, this pin is an output mode control pin (OM2) with

an internal 40 kΩ pull-up resistor. The OM2 pin, in conjunction with the OM0 and OM1 pins, allows

the user to select 1-of-8 output configurations (see Table 21). In SPI mode, this pin is an active low

chip select (CS) with no internal pull-up resistor.

OM1/SCLK

Digital Input. When the device is not in SPI mode, this pin is an output mode control pin (OM1) with

an internal 40 kΩ pull-up resistor. The OM1 pin, in conjunction with the OM0 and OM2 pins, allows

the user to select 1-of-8 output configurations (see Table 21). In SPI mode, this pin is the serial data

clock (SCLK) with no internal pull-up resistor.

OM0/SDIO

I/O

Digital Input/Output. When the device is not in SPI mode, this pin is an input only and functions as

an output mode control pin (OM0) with an internal 40 kΩ pull-up resistor. The OM0 pin, in

conjunction with the OM1 and OM2 pins, allows the user to select 1-of-8 output configurations (see

Table 21). In SPI mode, this pin is the serial data input/output (SDIO) with no internal pull-up

resistor.

RESET

Digital Input, Active Low with a 100 kΩ Internal Pull-Up Resistor. Resets the internal logic to default

states (see the Automatic Power-On Reset section).

FILTER

I/O

Loop Filter Node for the PLL. Connect external loop filter components (see Figure 22) from this pin

to Pin 17 (LDO).

17, 19

LDO

P/O

LDO Decoupling Pins. Connect a 0.47 μF decoupling capacitor from each of these pins to ground.

18, 21, 28

VDD

Power Supply Connection: 3.3 V Analog Supply.

LOCKED

Active High Locked Status Indicator for the PLL.

26, 22

OUT1, OUT2

Complementary Square Wave Clocking Outputs.

27, 23

OUT1, OUT2

Square Wave Clocking Outputs.

24, 25

GND

Ground.

Exposed die pad

The exposed die pad must be connected to GND.

1 I = input, I/O = input/output, O = output, P = power, and P/O = power/output.

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