AD9553SLASHPCBZ datasheet(26/44 Pages) AD

26 / 44 page

AD9553

Rev. 0 | Page 26 of 44

This leads to the complete frequency translation formula

⎟

⎠

⎞

⎜

⎝

⎛

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

OUT

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

OUT

Specific numeric constraints apply as follows. Note that the

symbol ∈ indicates that the constraint is an element of one in

the series from the list within the curly brackets.

{

}

∈

{}

1048576

{}

0 ∈

{}

∈

{}

∈

16384

∈

Additional constraints apply. One constraint is related to the

VCO and the other to the 2× frequency multipliers in the REFA

and REFB paths. The VCO constraint is a consequence of its

limited bandwidth. However, the 2× frequency multiplier

constraint only applies when the /5 prescalers are bypassed, but

it also requires that RA and RB are large enough to satisfy the

FPFD constraint. The additional constraints are as follows:

3350 MHz ≤ fOUT1 × P0 × P1 ≤ 4050 MHz

3350 MHz ≤ fOUT2 × P0 × P2 ≤ 4050 MHz

fREFA/B ≤ 125 MHz (2× multiplier with /5 bypassed)

Generally, the AD9553 is for applications in which fREFA and fREFB

are the same frequency, so the multiplexers in the REFA and

REFB paths share identical configurations. This, in conjunction

with the crystal frequency (fXTAL), results in the following

relationship between the RA and RXO dividers (here K is the scale

factor for the REFA path).

REFA

XTAL

Note that for pin-programmed holdover applications using the

crystal, the crystal frequency must be 25 MHz. Under these

circumstances, the above equation simplifies as follows:

REFA

× 6

CALCULATING DIVIDER VALUES

This section describes the process of calculating the divider

values when given a specific fOUT1/fREF ratio (fREF is the frequency

of either the REFA or REFB input signal source or the external

crystal resonator). This description is in general terms, but it

includes a specific example for clarity. The example assumes

a frequency control pin setting of A[3:0] = 1011 (see Table 14)

and Y[5:0] = 011100 (see Table 15), yielding the following:

fREF = 125 MHz

fOUT1 = 155.52 MHz

Follow these steps to calculate the divider values.

Determine the output divide factor (ODF).

Note that the VCO frequency (fVCO) spans 3350 MHz to

4050 MHz. The ratio, fVCO/fOUT1, indicates the required

ODF. Given the specified value of fOUT1 (155.52 MHz)

and the range of fVCO, the ODF spans a range of 21.54 to

26.04. The ODF must be an integer, which means that ODF

is 22, 23, 24, 25, or 26.

Determine suitable values for P0, P1 and fVCO.

The ODF is the product of the two output dividers P0 and

P1 (ODF = P0P1). However, P0 is constrained to 5 or 6 (see

the Output/Input Frequency Relationship section), which

means that there are only two possibilities for ODF in this

example: ODF = 24 (P0 = 6, P1 = 4) and ODF = 25 (P0 = 5,

P1 = 5). These two ODF values result in the only VCO

frequencies that satisfy the 155.52 MHz requirement for

OUT1 (3732.48 MHz for ODF = 24 and 3888 MHz for

ODF = 25). The results appear below. Note that the first

result agrees with Table 15 in the Preset Frequencies

section).

P0 = 6, P1 = 4 (fVCO = 3732.48 MHz)

P0 = 5, P1 = 5 (fVCO = 3888 MHz)

Determine the boundary conditions on N, K, and R.

Because of the architecture of the PLL, FPFD must be an

integer submultiple of the VCO frequency as shown in the

following equation. Note that N is an integer and is the

20-bit value of the N-divider.

FPFD

VCO

This relationship leads to boundary conditions on N

because N must be an integer that satisfies N = fVCO/FPFD.

The limits on FPFD (13.3 kHz to 100 MHz) combined with

the results for fVCO from Step 2 yield

N = 38...280,637 (for fVCO = 3732.48 MHz)

N = 39...292,330 (for fVCO = 3888 MHz)

Note that FPFD also relates to the input frequency, fREF, per

the following equation. Here, R is the 14-bit integer divi-

sion factor of the input divider (RA or RB), while K is the

scale factor associated with the optional 2× multiplier and

divide-by-five functions. Note that K can only be one of

four values: 1/5, 2/5, 1, or 2.

⎟

⎠

⎞

⎜

⎝

⎛

FPFD

REF

This relationship leads to boundary conditions on R because

R/K = fREF/FPFD where R must be an integer and K can only

be 1/5, 2/5, 1, or 2. The limits on FPFD (13.3 kHz to 100

MHz) combined with the given value of fREF yield the

following bounds on R. Note that for K = 2, the upper bound

on R is limited by its 14-bit range.

AD9553/PCBZ Datasheet(PDF) 26 Page - Analog Devices

AD9553/PCBZ Datasheet(HTML) 26 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Datasheet Descarga

Enlace URL