AD9553SLASHPCBZ datasheet(25/44 Pages) AD

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AD9553

Rev. 0 | Page 25 of 44

Output Driver Polarity (CMOS)

When the mode control bits indicate the CMOS logic family

(see Table 19), the user has control of the logic polarity asso-

ciated with each CMOS output pin. Driver polarity defines how

the logic level (Logic 1 or Logic 0) at a CMOS output pin relates

to the logic state (Logic True or Logic False). Normal polarity

equates Logic 1/Logic 0 to Logic True/Logic False, while

inverted polarity equates Logic 0/Logic 1 to Logic True/Logic

False. Bits[2:1] of the OUT1 and OUT2 driver control registers

control the CMOS polarity of the associated output driver (see

Figure 23).

Output Drive Strength (CMOS or LVDS)

When the mode bits indicate the CMOS or LVDS logic family

(see Table 19), the user can select whether the output driver

uses weak or strong drive capability. Bit 7 of the OUT1 and

OUT2 driver control registers control the drive strength of the

associated output driver (see Figure 23). In the case of the

CMOS family, the strong setting allows for driving increased

capacitive loads. In the case of the LVDS family, the nominal

weak and strong drive currents are 3.5 mA and 7 mA,

respectively.

Output Power Down

The AD9553 supports the option of independent power-down

of the output drivers. Bit 6 of the OUT1 and OUT2 driver control

registers controls the power-down function (see Figure 23). When

Bit 6 is Logic 0, the associated output driver is active. When Bit 6 is

Logic 1, the associated output driver is in power-down mode.

JITTER TOLERANCE

Jitter tolerance is the ability of the AD9553 to maintain lock in

the presence of sinusoidal jitter. The AD9553 meets the input

jitter tolerance mask per Telcordia GR-253-CORE (see Figure 24).

The acceptable jitter tolerance is the region above the mask. The

trace showing the performance of the AD9553 in Figure 24

represents the limitations of the test equipment because the

AD9553 did not indicate loss of lock, even with the test

equipment injecting its maximum jitter level.

100

0.1

0.01

0.1

100

10k

JITTER FREQUENCY (kHz)

AD9553

MASK

Figure 24. Jitter Tolerance

OUTPUT/INPUT FREQUENCY RELATIONSHIP

The frequency at OUT1 and OUT2 depends on the frequency

at the input to the PLL, the PLL feedback divider value (N), and

the output divider values (P0, P1, and P2). The equations that

define the frequency at OUT1 and OUT2 (fOUT1 and fOUT2,

respectively) are as follows:

⎟

⎠

⎞

⎜

⎝

⎛

FPFD

OUT

⎟

⎠

⎞

⎜

⎝

⎛

FPFD

OUT

where:

FPFD is the frequency at the reference input of the PFD.

N is the feedback divider value.

P0 is the VCO prescaler divider value.

P1 is the OUT1 divider value.

P2 is the OUT2 divider value.

The operating frequency range of the PFD places a limitation

on FPFD as follows:

13.3 kHz ≤

FPFD ≤ 100 MHz

Note that for applications using the frequency selection pins in

conjunction with the XTAL input for the holdover function, the

maximum value of FPFD is 50 MHz (twice the 25 MHz default

crystal frequency).

FPFD depends on the input frequency to the AD9553, the

configuration of the multiplexers for the /5 prescaler and 2×

frequency multiplier, and the value of the RX divider (either RA,

RB, or RXO) as follows:

FPFD

where:

fX is equal to fREFA, fREFB, or fXTAL.

K is the scale factor per Table 22.

FPFD is the frequency at the input to the phase frequency

detector.

Table 22. K as a Function of Input Multiplexer Configuration

Input

2×

REFA

Bypassed

Active

Bypassed

1/5

Bypassed

Active

2/5

REFB

Bypassed

Active

Bypassed

1/5

Bypassed

Active

2/5

XTAL

N/A

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