AD9553SLASHPCBZ datasheet(7/44 Pages) AD

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AD9553

Rev. 0 | Page 7 of 44

JITTER CHARACTERISTICS

Table 9.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

JITTER GENERATION

12 kHz to 20 MHz

LVPECL Output

1.31

ps rms

Input = 122.88 MHz, output = 155.52 MHz.

LVDS Output

1.32

ps rms

Input = 122.88 MHz, output = 155.52 MHz.

CMOS Output

1.24

ps rms

Input = 122.88 MHz, output = 155.52 MHz.

LVPECL Output

1.28

ps rms

Input = 19.44 MHz, output = 245.76 MHz.

LVDS Output

1.29

ps rms

Input = 19.44 MHz, output = 245.76 MHz.

CMOS Output

1.26

ps rms

Input = 19.44 MHz, output = 245.76 MHz. See Figure 12 regarding

CMOS toggle rates above 250 MHz.

50 kHz to 80 MHz

Input = 122.88 MHz, output = 155.52 MHz.

LVPECL Output

0.44

ps rms

Input = 122.88 MHz, output = 155.52 MHz.

LVDS Output

0.45

ps rms

Input = 122.88 MHz, output = 155.52 MHz.

CMOS Output

0.39

ps rms

Input = 122.88 MHz, output = 155.52 MHz.

LVPECL Output

0.75

ps rms

Input = 19.44 MHz, output = 245.76 MHz.

LVDS Output

0.76

ps rms

Input = 19.44 MHz, output = 245.76 MHz.

CMOS Output

0.44

ps rms

Input = 19.44 MHz, output = 245.76 MHz. See Figure 12 regarding

CMOS toggle rates above 250 MHz.

JITTER TRANSFER BANDWIDTH

See the Typical Performance Characteristics section.

Low BW Setting

170

Applies to all input frequency pin programming configurations that

use 170 Hz loop bandwidth per Table 17.

High BW Setting

kHz

Applies to all input frequency pin programming configurations that

use 75 kHz loop bandwidth per Table 17.

JITTER TRANSFER PEAKING

See the Typical Performance Characteristics section

Low BW Setting

1.3

Applies to all input frequency pin programming configurations that

use 170 Hz loop bandwidth per Table 17.

High BW Setting

0.08

Applies to all input frequency pin programming configurations that

use 75 kHz loop bandwidth per Table 17.

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