AD9553SLASHPCBZ datasheet(21/44 Pages) AD

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AD9553

Rev. 0 | Page 21 of 44

REG 0x29[7:6]

REVERTIVE

NON-REVERTIVE

SELECT REFA

SELECT REFB

REVERTIVE/

NON-REVERTIVE

LOGIC

SPI SELECT REFA/B

LOGIC

SEL

REFB

FROM REFA

INPUT

FROM REFB

INPUT

FROM XTAL

INPUT

SIGNAL

DETECTOR

REFA PRESENT

REFB PRESENT

XTAL PRESENT

REFA/B

SELECTION LOGIC

MUX

CONTROL

LOGIC

PLL

SEL B/A

FDBK

CLOCK

MUX

RA DIVIDER

RB DIVIDER

RXO DIVIDER

Figure 21. Switchover/Holdover Block Diagram

The user can override the automatic switchover functions

(revertive and nonrevertive) and manually select the REFA

or REFB signal by programming Register 0x29[7:6] = 10 or 11,

respectively. Note, however, that the desired signal (REFA or

REFB) must be present for the device to select it.

The user can also force the device to switch to REFB by

applying a Logic 1 to the external SEL REFB pin. This overrides

a REFA selection invoked by either the revertive/nonrevertive

logic or when Register 0x29[7:6] = 10. Note, however, that

REFB must be present to be selected by the device.

PLL (PFD, Charge Pump, VCO, Feedback Divider)

The PLL (see Figure 20) consists of a phase-frequency detector

(PFD), a partially integrated analog loop filter (see Figure 22),

an integrated voltage-controlled oscillator (VCO), and a 20-bit

programmable feedback divider. The PLL generates a 3.35 GHz

to 4.05 GHz clock signal based on the frequency of FPFD (see

Figure 20) and the feedback divider value, which is phase-

locked to the input reference signal.

The PFD of the PLL drives a charge pump that increases,

decreases, or holds constant the charge stored on the loop filter

capacitors (both internal and external). The stored charge results

in a voltage that sets the output frequency of the VCO. The

feedback loop of the PLL causes the VCO control voltage to

vary in such a way as to phase lock the PFD input signals. Note

that the PFD supports input frequencies spanning 13.3 kHz to

100 MHz (implying that input frequencies between 8 kHz and

13.3 kHz must use the 2× frequency multiplier in the input path).

The PLL has a VCO with 128 frequency bands spanning a range

of 3350 MHz to 4050 MHz (3700 MHz nominal). However, the

actual operating frequency within a particular band depends on

the control voltage that appears on the loop filter capacitor. The

control voltage causes the VCO output frequency to vary linearly

within the selected band. This frequency variability allows the

control loop of the PLL to synchronize the VCO output signal

with the reference signal applied to the PFD.

Typically, selection of the VCO frequency band (as well as gain

adjustment) occurs automatically as part of the device’s automatic

VCO calibration process, which initiates at power up (or reset).

Alternatively, the user can force VCO calibration by first

enabling SPI control of VCO calibration (Register 0x0E[2] = 1)

and then writing a 1 to the calibrate VCO bit (Register 0x0E[7]).

To facilitate system debugging, the user can override the VCO

band setting by first enabling SPI control of VCO band

(Register 0x0E[0] = 1) and then writing the desired value to

The feedback divider (N-divider) sets the frequency multi-

plication factor of the PLL in integer steps over a 20-bit range.

However, the N-divider has a lower limit of 32, which sets a

minimum PLL multiplication factor of 32.

AD9553/PCBZ Datasheet(PDF) 21 Page - Analog Devices

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