MPC8378E datasheet(38/128 Pages) FREESCALE

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MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

Freescale Semiconductor

This figure shows the MII management AC timing diagram.

Figure 20. MII Management Interface Timing Diagram

9USB

This section provides the AC and DC electrical characteristics for the USB dual-role controllers.

MDC rise time (20%–80%)

tMDCR

——

MDC fall time (80%–20%)

tMDCF

——

Notes:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX

symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are

invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input

signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For

rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. This parameter is dependent on the system clock speed.

3. Guaranteed by design.

4. tplb_clk is the platform (CSB) clock divided according to the SCCR[TSEC1CM].

Table 38. MII Management AC Timing Specifications (continued)

Parameter

Symbol1

Min

Typical

Max

Unit

Note

MDC

tMDDXKH

tMDC

tMDCH

tMDCR

tMDCF

tMDDVKH

tMDKHDX

MDIO

(Input)

(Output)

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