MPC8378E datasheet(42/128 Pages) FREESCALE

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MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

Freescale Semiconductor

Local bus clock to output high impedance for LAD/LDP

tLBKHOZ

—

3.8

3, 8

Output hold from local bus clock for LAD/LDP

tLBKHOX

1—

Notes:

1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1

symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes

high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go

high (H), with respect to the output (O) going invalid (X) or output hold time.

2. All timings are in reference to rising edge of LSYNC_IN at LBVDD/2 and the 0.4 × LBVDD of the signal in question.

3. All signals are measured from LBVDD/2 of the rising/falling edge of LSYNC_IN to 0.5 × LBVDD of the signal in question.

4. Input timings are measured at the pin.

5. tLBOTOT1 should be used when LBCR[AHD] is set and the load on LALE output pin is at least 10pF less than the load on

LAD output pins.

6. tLBOTOT2 should be used when LBCR[AHD] is not set and the load on LALE output pin is at least 10pF less than the load

on LAD output pins.

7. tLBOTOT3 should be used when LBCR[AHD] is not set and the load on LALE output pin equals to the load on LAD output pins.

8. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

Table 44. Local Bus General Timing Parameters—PLL Enable Mode (continued)

Parameter

Symbol1

Min

Max

Unit

Note

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