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MPC8378E Datasheet(PDF) 79 Page - Freescale Semiconductor, Inc |
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MPC8378E Datasheet(HTML) 79 Page - Freescale Semiconductor, Inc |
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79 / 128 page ![]() MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8 Freescale Semiconductor 79 This figure shows the SPI timing in master mode (internal clock). Figure 53. SPI AC Timing in Master Mode (Internal Clock) Diagram 20 High-Speed Serial Interfaces (HSSI) This chip features two serializer/deserializer (SerDes) interfaces to be used for high-speed serial interconnect applications. See Table 1 for the interfaces supported. This section describes the common portion of SerDes DC electrical specifications, which is the DC requirement for SerDes reference clocks. The SerDes data lane’s transmitter and receiver reference circuits are also shown. 20.1 Signal Terms Definition The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms used in the description and specification of differential signals. Figure 54 shows how the signals are defined. For illustration purpose, only one SerDes lane is used for description. The figure shows waveform for either a transmitter output (SDn_TX and SDn_TX) or a receiver input (SDn_RX and SDn_RX). Each signal swings between A volts and B volts where A > B. Using this waveform, the definitions are as follows. To simplify illustration, the following definitions assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signaling environment. • Single-Ended Swing The transmitter output signals and the receiver input signals SDn_TX, SDn_TX, SDn_RX and SDn_RX each have a peak-to-peak swing of A – B volts. This is also referred as each signal wire’s single-ended swing. • Differential Output Voltage, VOD (or Differential Output Swing): The differential output voltage (or swing) of the transmitter, VOD, is defined as the difference of the two complimentary output voltages: VSDn_TX – VSDn_TX. The VOD value can be either positive or negative. SPICLK (output) tNIIXKH tNIKHOV Input Signals: SPIMISO (See Note) Output Signals: SPIMOSI (See Note) Note: The clock edge is selectable on SPI. tNIIVKH |
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