MPC8378E datasheet(52/128 Pages) FREESCALE

52 / 128 page

MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

Freescale Semiconductor

11.2.1

Full-Speed Output Path (Write)

This figure provides the data and command output timing diagram.

Figure 31. Full Speed Output Path

11.2.1.1

Full-Speed Write Meeting Setup (Maximum Delay)

The following equations show how to calculate the allowed skew range between the SD_CLK and

SD_DAT/CMD signals on the PCB.

No clock delay:

tSFSKHOV + tDATA_DELAY + tISU < tSFSCKL

Eqn. 1

With clock delay:

tSFSKHOV + tDATA_DELAY + tISU < tSFSCKL + tCLK_DELAY

Eqn. 2

tDATA_DELAY + tSFSCKL < tSFSCK + tCLK_DELAY – tISU – tSFSKHOV

Eqn. 3

This means that data can be delayed versus clock up to 11 ns in ideal case of tSFSCKL =20 ns:

tDATA_DELAY + 20 < 40 + tCLK_DELAY – 5 – 4

tDATA_DELAY < 11 + tCLK_DELAY

11.2.1.2

Full-Speed Write Meeting Hold (Minimum Delay)

The following equations show how to calculate the allowed skew range between the SD_CLK and

SD_DAT/CMD signals on the PCB.

tCLK_DELAY < tSFSCKL + tSFSKHOX + tDATA_DELAY – tIH

Eqn. 4

Input at the

MPC8378E pins

SD CLK at the

MPC8378E pin

Output valid time: tSFSKHOV

Output hold time: tSFSKHOX

tIH (5 ns)

tCLK_DELAY

SD CLK at

Driving

Edge

Sampling

edge

the card pin

tISU (5 ns)

tDATA_DELAY

tSFSCKL

tSFSCK (clock cycle)

Output from the

MPC8378E Pins

MPC8378E Datasheet(PDF) 52 Page - Freescale Semiconductor, Inc

MPC8378E Datasheet(HTML) 52 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL