MPC8378E datasheet(19/128 Pages) FREESCALE

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MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

Freescale Semiconductor

This table provides the input AC timing specifications for the DDR1 and DDR2 SDRAM interface.

6.2.2

DDR1 and DDR2 SDRAM Output AC Timing Specifications

This table shows the DDR1 and DDR2 SDRAM output AC timing specifications.

Table 20. DDR1 and DDR2 SDRAM Input AC Timing Specifications

Parameter

Symbol

Min

Max

Unit

Note

Controller skew for MDQS-MDQ/MECC/MDM

400 MHz data rate

333 MHz data rate

266 MHz data rate

tCISKEW

–500

–750

500

750

1, 2

—

Note:

1. tCISKEW represents the total amount of skew consumed by the controller between MDQSn and any corresponding bit that

will be captured with MDQS

n. This should be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be

determined by the following equation: tDISKEW = ±[T/4 – |tCISKEW|] where T is the MCK clock period and |tCISKEW| is the

absolute value of tCISKEW.

3. This specification applies only to DDR2 interface.

Table 21. DDR1 and DDR2 SDRAM Output AC Timing Specifications

Parameter

Symbol1

Min

Max

Unit

Note

MCK

n cycle time, MCKn/MCKn crossing

tMCK

510

ADDR/CMD output setup with respect to MCK

400 MHz data rate

333 MHz data rate

266 MHz data rate

200 MHz data rate

tDDKHAS

1.95

2.40

3.15

4.20

—

3, 7

ADDR/CMD output hold with respect to MCK

400 MHz data rate

333 MHz data rate

266 MHz data rate

200 MHz data rate

tDDKHAX

1.95

2.40

3.15

4.20

—

3, 7

MCS

n output setup with respect to MCK

400 MHz data rate

333 MHz data rate

266 MHz data rate

200 MHz data rate

tDDKHCS

1.95

2.40

3.15

4.20

—

MCS

n output hold with respect to MCK

400 MHz data rate

333 MHz data rate

266 MHz data rate

200 MHz data rate

tDDKHCX

1.95

2.40

3.15

4.20

—

MCK to MDQS skew

tDDKHMH

–0.6

0.6

4, 8

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