WM8741GEDSSLASHV datasheet(34/64 Pages) WOLFSON

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WM8741

Production Data

PD, Rev 4.2, October 2009

ZERO FLAG OUTPUT

The WM8741 has one zero flag output pin, ZFLAG (pin 21). The zero flag feature is only valid for

PCM data.

The WM8741 asserts Logic 1 on the ZFLAG pin when a sequence of more than 1024 zeros is input

to the chip. The default value is a logical AND of both left and right channels. Under software

control, the user can also set the zero flag pin to respond to either the left channel OR the right

channel.

The zero flag pin can be used to control external muting circuits if required.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Volume Control

04h

6:5

ZEROFLR

[1:0]

Zero flag output:

00 = Pin assigned to logical AND of

LEFT and RIGHT channels

01 = Pin assigned to LEFT channel

10 = Pin assigned to RIGHT

channel

11 = ZFLAG disabled

Table 32 Zero Flag Output

ZFLAG FORCE HIGH CONTROL

It is possible to force the ZFLAG pin to Logic 1 by setting ZFLAG_HI=1 in R7. This is useful in

situations where an application processor may require manual control of an external mute circuit.

Setting ZFLAG_HI=0 will allow the ZFLAG pin to function as defined by ZFLAGLR[1:0].

BIT

LABEL

DEFAULT

DESCRIPTION

Mode Control 1

06h

ZFLAG_HI

ZFLAG Force High Control

0 = Normal operation

1 = Output Logic 1

Table 33 ZFLAG Force High Control

INFINITE ZERO DETECT

The IZD register configures the operation of the WM8741 analogue mute in conjunction with the zero

flag feature. Table 20 shows the interdependency of the MUTEB pin, the IZD register and the zero

flag.

BIT

LABEL

DEFAULT

DESCRIPTION

Volume Control

04h

IZD

IZD control of analogue mute:

0 = Never analogue mute

1 = Analogue mute when ZFLAG

set

Table 20 Infinite Zero Detect Control

WM8741GEDS/V Datasheet(PDF) 34 Page - Wolfson Microelectronics plc

WM8741GEDS/V Datasheet(HTML) 34 Page - Wolfson Microelectronics plc

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