AN2647 datasheet(12/34 Pages) STMICROELECTRONICS

12 / 34 page

Interfacing with asynchronous memory

AN2647

12/34

Figure 7.

Read bus cycle, non-multiplexed bus

EMI_RD Signal Configuration

The EMI_RD signal's timing is controlled by the WSTRD value in the EMI_RCRx register

(Read Wait State Control) and the WSTOEN value in the EMI_OECRx register (Output

Enable Control).

●

WSTOEN: Read Enable. WSTOEN specifies the delay between the assertion of the

chip select and EMI_RDn goes low. The delay is defined in terms of BCLK clock

periods.The minimum WSTOEN value is 0 in a non-Multiplexed bus, EMI_RDn can be

active at the same time as the CSx signal.

●

WSTRD: Read wait state. WSTRD specifies the pulse width, or the rising edge of

EMI_RDn. The pulse width is defined in terms of BLCK periods and is = (WSTRD-

WSTOEN+1)The choice of WSTRD value depends on the access time of the memory

device, slow memory requires more wait states. Typically, the memory access time

must meet the following condition:

Memory Read access time < (tRAS + tRP - tRDS)

where tRAS is the read address setup time, tRP is the EMI_RDn pulse width and tRDS is the

data setup time.

The read bus cycle in Figure 7. has the following configuration:

WSTOEN = 1

WSTRD = 1

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